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Array substrate and its preparation method

An array substrate and substrate technology, applied in the field of array substrate and its preparation, can solve the problems of poor display performance of display devices

Active Publication Date: 2021-08-27
BOE TECH GRP CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] The present invention at least partly solves the problem of poor display performance of existing display devices, and provides an array substrate with excellent performance to form a display device with excellent performance

Method used

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  • Array substrate and its preparation method

Examples

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Embodiment 1

[0029] like figure 1 , Figures 2a to 2d As shown, this embodiment provides an array substrate, including:

[0030] base 10;

[0031] The first transistor 20 disposed on the substrate 10 includes a first active layer 21 formed of a low-temperature polysilicon material;

[0032] The second transistor 30 disposed on the side of the first transistor 20 away from the substrate 10 includes a second active layer 31 formed of a metal oxide semiconductor material;

[0033] The barrier layer 40 is located between the first transistor 20 and the second transistor 30 , and the barrier layer 40 is used to prevent the hydrogen element in the first active layer 21 from diffusing into the second active layer 31 .

[0034] Wherein, that is to say, the array substrate of this embodiment has at least two types of transistors: low-temperature polysilicon transistors and metal oxide transistors, that is, the first transistor 20 is a low-temperature polysilicon transistor with a first active la...

Embodiment 2

[0051] like figure 1 , Figures 2a to 2d As shown, this embodiment provides a method for preparing an array substrate, which is the method for preparing a display substrate in Embodiment 1, including:

[0052] S11 , forming a first transistor 20 on the substrate 10 .

[0053] Specifically, S111, such as Figure 2a As shown, a first active layer 21 of low temperature polysilicon, a first gate insulating layer, a first gate layer 24 , and a third conductive layer 53 disposed on the same layer as the first gate layer 24 are formed on the substrate 10 .

[0054] Wherein, the first active layer 21 is formed by laser rapid annealing process, and the first gate insulating layer and the first gate layer 24 are simultaneously formed by self-alignment process.

[0055] S112, such as Figure 2b As shown, an interlayer dielectric layer 64 (ILD) is formed on the first active layer 21, the first gate insulating layer, the first gate layer 24, and the third conductive layer 53 to form th...

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Abstract

The invention provides an array substrate and a preparation method thereof, belonging to the field of display technology, which can at least partly solve the problem of poor display performance of existing display devices. An array substrate of the present invention comprises: a substrate; a first transistor disposed on the substrate, including a first active layer formed of a low-temperature polysilicon material; a second transistor disposed on the side of the first transistor away from the substrate, comprising a The second active layer formed of metal oxide semiconductor material; the barrier layer, located between the first transistor and the second transistor, the barrier layer is used to prevent the hydrogen element in the first active layer from diffusing into the second active layer.

Description

technical field [0001] The invention belongs to the field of display technology, and in particular relates to an array substrate and a preparation method thereof. Background technique [0002] In a display device with thin film transistors in the prior art, LTPO technology is used, that is, a combination of low temperature polysilicon (LTPS) thin film transistors and metal oxide (Metal Oxide) thin film transistors, which enables the display device to have high resolution. (PPI), low power consumption, high image quality and other advantages. Specifically, since the low-temperature polysilicon thin film transistor has high mobility characteristics, the charging speed of the pixel capacitance in the display device can be increased; at the same time, the display performance of the display device can be further improved due to the low current leakage rate of the metal oxide thin film transistor . [0003] The steps of forming the display device are as follows: firstly forming ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/12H01L21/77
CPCH01L27/1225H01L27/1259
Inventor 王国英宋振
Owner BOE TECH GRP CO LTD
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