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How to create and operate lateral diffusion mosfets

A lateral, area technology used in laterally diffused MOSFETs. field

Active Publication Date: 2022-04-22
AVAGO TECH INT SALES PTE LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the LDD segment also increases the resistance of the LDMOS in the on-state (on resistance), which can be a problem in applications where fast turn-on of the LDMOS is required

Method used

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  • How to create and operate lateral diffusion mosfets
  • How to create and operate lateral diffusion mosfets
  • How to create and operate lateral diffusion mosfets

Examples

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Embodiment Construction

[0010] The detailed description set forth below is intended as a description of various configurations of the technology and is not intended to represent the only configurations in which the technology may be practiced. The accompanying drawings are incorporated herein and constitute a part of the detailed description. The detailed description includes specific details to provide a thorough understanding of the technology. However, the technology is not limited to the specific details set forth herein and may be practiced without one or more of the specific details. In some instances, structures and components are shown in block diagram form in order to avoid obscuring the concepts of the technology.

[0011] In one or more aspects of the present technology, systems and configurations for providing LDMOS on FDSOI are described. FDSOI can be used in high-performance processors because it can provide ultra-low power electronics with significantly reduced leakage power. The ch...

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PUM

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Abstract

The present invention provides laterally diffused MOSFETs on fully depleted SOI with low on-resistance. A laterally diffused MOSFET includes a substrate and a first semiconductor layer disposed on the substrate. The laterally diffused MOSFET also includes a buried oxide layer disposed on the first semiconductor layer. A second semiconductor layer including a first gate region, a drain region and a source region is disposed on the buried oxide layer. The first gate region is positioned between the source region and the drain region. A first shallow trench isolation is disposed between the drain region and the first semiconductor layer. A second gate region is disposed on the first semiconductor layer away from the second semiconductor layer and between the first and second shallow trench isolations. A gate node is coupled to the first and second gate regions to apply a gate voltage to the first and second gate regions.

Description

technical field [0001] This description relates generally to integrated circuits, and more particularly to laterally diffused MOSFETs. Background technique [0002] Laterally diffused MOSFETs (LDMOS) on fully depleted SOI (FDSOI) are receiving increasing attention in the semiconductor industry due to their need for smaller dimensions compared to bulk LDMOS. Designing LDMOS on FDSOI can form a drain that contains lightly doped segments. Lightly doped drain (LDD) segments provide a voltage drop from the drain to the edge of the gate, which can help prevent gate dielectric breakdown. Therefore, LDMOS on FDSOI can support a higher breakdown voltage than bulk LDMOS. However, the LDD segment also increases the resistance of the LDMOS in the on-state (on resistance), which can be a problem in applications where fast turn-on of the LDMOS is required. Therefore, it is highly desirable to provide an LDMOS with low resistance on FDSOI in the on-state. Contents of the invention ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L23/528H01L21/768H01L21/336
CPCH01L29/7824H01L29/66681H01L23/5283H01L21/76805H01L21/76895H01L29/513H01L29/78624H01L29/78648H01L29/0886H01L21/76275H01L21/76283H01L29/0653H01L29/0878H01L21/31111H01L29/0882
Inventor 清·刘伊藤明肖姆·苏伦德兰·波诺斯
Owner AVAGO TECH INT SALES PTE LTD
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