FPGA service system, data processing method and storage medium

Abstract

The invention provides an FPGA service system, a data processing method and a storage medium. A first bus interface which is universal to the outside is arranged, no matter what type of FPGA platformon which the FPGA service system is deployed, a user directly connects designed functional hardware for realizing a certain service to the first bus interface; communication control equipment of the FPGA service system can ensure reliable work of the functional hardware; therefore, the FPGA service system can reliably provide the business service for the outside. A user does not need to design a plurality of functional hardware for realizing the same service for different types of FPGA platforms, so that the transplanting cost and time and effort of the FPGA service system on each FPGA platform are reduced, and the service development flexibility and efficiency are improved.

Description

Technical field [0001] This application mainly relates to the field of cloud service applications, and more specifically to an FPGA service system, data processing method and storage medium. Background technique [0002] FPGA (Field-Programmable Gate Array) is a product of further development on the basis of programmable devices. It usually appears as a semi-custom circuit in the field of Application Specific Integrated Circuit (ASIC). It not only solves the shortcomings of customized circuits, but also overcomes the shortcomings of the limited number of gate circuits of the original programmable device. [0003] At present, in order to shorten the development time of users, FPGA chip manufacturers will provide users with different functional IP cores (Intellectual Property core, intellectual property core), which is convenient for users to directly select corresponding functional IP cores for integration according to functional design requirements, which improves user design effe...

AI Technical Summary

Problems solved by technology

However, the on-chip bus standards (i.e., bus protocols) followed by the IP cores produced by various FPGA chip manufacturers are not uniform, and the interface and timing of the IP cores are also very different, which leads users to build and realize certain business functions on the FPGA platform. In the hardware process, there are great constraints on chip selection and hardware and software design

[0004] Moreover, when the user wants to apply the functional hardware designed

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