Multi-chip package structure and manufacturing method thereof
A technology of multi-chip packaging and manufacturing methods, which is applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device parts, semiconductor devices, etc., can solve the problems of large interconnection distance between multiple chips in packaging volume, and achieve high production capacity and signal delay The effect of small size and small package volume
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[0038] In the following description, the present invention is described with reference to various examples. One skilled in the art will recognize, however, that the various embodiments may be practiced without one or more of the specific details, or with other alternative and / or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail so as not to obscure aspects of the various embodiments of the invention. Similarly, for purposes of explanation, specific quantities, materials and configurations are set forth in order to provide a thorough understanding of embodiments of the invention. However, the invention may be practiced without these specific details. Furthermore, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.
[0039] In this specification, reference to "one embodiment" or "the...
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