A High Linearity Delay Chain

Abstract

A high linearity delay chain includes a calibration module, a delay chain module and a first multiplexer, the delay chain module includes 2 n ‑1 cascaded delay unit, each delay unit consists of 2 m A delay path and a second multiplexer, each delay path outputs the input signal of the delay unit to the second multiplexer after different delays; the second multiplexer is selected according to the m-bit calibration code The signal output after passing through the corresponding delay path; the clock terminal of the calibration module is connected to the clock signal, and the calibration terminal is connected to the output terminal of the last delay unit in the cascade, which is used to generate an m-bit calibration code, and when the rising edge of the clock signal arrives Determine whether the calibration code is plus one or minus one and send the input signal of the delay chain to the input end of the first delay unit in the delay chain module; the input end of the first multiplexer is connected to the input end of the delay chain module and 2 n The output terminal of 1 delay unit, the selection terminal of which is connected to the n-bit selection signal, and the output terminal is used as the output terminal of the delay chain.

Description

technical field [0001] The invention belongs to the technical field of power electronics, and in particular relates to a delay chain with high linearity. Background technique [0002] As modern technology enters the nanometer level, and the integration of circuits is getting higher and higher, and the frequency of circuits is getting faster and faster, so the optimization of timing is becoming more and more important. The delay chain structure is a typical timing structure. There are more and more digital circuits in the delay chain structure, and the requirements for the precision and linearity of the delay chain structure are also getting higher and higher. The delay chain structure has a wide range of applications, and has applications in many different structures such as phase-locked loops, digital pulse width modulators, FPGAs, and DC-DC converters. In the traditional delay chain structure, a single delay unit can only implement two delay paths, and the linearity is no...

AI Technical Summary

Problems solved by technology

[0003] Aiming at the problem of low linearity in the above-mentioned traditional delay chain, the present invention proposes a delay chain, which introduces a multiplexer into a single delay unit, so that the delay unit can realize multiple delays, and at the same time use the same calibration code to control Each delay unit makes the delay time of each delay unit the same, and realizes outputting a delayed signal with high linearity

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