Operational-amplifier-free MDAC type time domain ADC structure

Abstract

The invention belongs to the field of integrated circuits, and particularly relates to an operational-amplifier-free MDAC type time domain ADC structure. A voltage domain analog-to-digital converter module, a digital-to-analog converter module, a residual error operation array module and a time domain analog-to-digital converter module are sequentially connected. The output end of the voltage domain analog-to-digital converter module is also connected with the digital decoding and calibration module. The output end of the time domain analog-to-digital converter module is connected with the digital decoding and calibration module. The signal output end is connected with the input ends of the voltage domain analog-to-digital converter module and the residual error operation array module. Thereference voltage output end is connected with the reference voltage input ends of the voltage domain analog-to-digital converter module and the digital-to-analog converter module. A clock control signal output end is connected with clock input ends of the voltage domain analog-to-digital converter module, the analog-to-digital converter module, the residual error operation array module and the time domain analog-to-digital converter module. The structure has the beneficial effects of high speed, high precision, low power consumption and small system area.

Description

technical field [0001] The invention belongs to the field of integrated circuits, and in particular relates to an MDAC time-domain ADC structure without an operational amplifier. Background technique [0002] The analog-to-digital converter unit circuit of optical pulse or millimeter wave radar system and wireless communication system plays an important role in the whole system. New developments have required a sampling rate in the G Hz range and a resolution of more than 10 bits. With the entry of CMOS technology into deep sub-micron systems, the voltage resolution can be surpassed by the time edge resolution. In the current high-speed / ultra-high-speed ADC architecture research, the analog voltage signal in the voltage domain is converted into a digital pulse width signal in the time domain. Processing is a new research trend. Under the same speed and accuracy, the area and power consumption of time-domain ADCs are unmatched by traditional voltage-domain ADCs. The perfor...

AI Technical Summary

Problems solved by technology

Due to the use of a residual amplifier in this ADC, the linearity of the ADC is reduced, and the noise and power consumption are large, and because the gain error and common-mode offset caused by capacitance mismatch need to be considered when adding a residual amplifier, the design of the ADC is difficult.

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