Fan-out chip packaging structure and packaging method

A chip packaging structure and chip packaging technology, applied in the direction of electrical components, electric solid devices, circuits, etc., can solve the problems of low reliability of packaging structure, stress fracture failure, etc. , the effect of improving reliability
CN110517992AActive Publication Date: 2019-11-29江苏中科智芯集成科技有限公司
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
江苏中科智芯集成科技有限公司
Publication Date
2019-11-29

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Abstract

The invention discloses a fan-out chip packaging structure and a packaging method. The packaging structure comprises a plastic packaging body, an interconnection layer and a rewiring layer, wherein the plastic packaging body is internally packaged with at least one chip, and the device surface of the chip is exposed out of the plastic packaging body; the interconnection layer is arranged on the surface of the device surface of the plastic packaging body and is internally provided with a conductive convex point corresponding to a pad of the chip, and the conductive convex point is used for leading out the corresponding pad to the upper surface of the interconnection layer; and the rewiring layer is arranged on the interconnection layer, and the rewiring layer is electrically coupled with the convex point. As the interconnection layer is arranged between the rewiring layer and the plastic packaging body, the interface stress between the plastic packaging body and the chip is greatly reduced after passing through the interconnection layer, the stress borne by the rewiring layer can be greatly reduced, the possibility of fatigue fracture due to the influence of the interface stress onthin and narrow rewiring is greatly reduced, and the reliability of the packaging structure is improved.
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Description

technical field

[0001] The invention relates to the technical field of semiconductor integrated circuit packaging, in particular to a fan-out chip packaging structure and packaging method. Background technique

[0002] As the most cost-effective technology in the field of system integration packaging, wafer-level fan-out packaging technology will gradually lead the development direction of future system integration technology by virtue of its advantages of high density, light weight and short size, good heat dissipation performance and good electrical performance. . At present, fan-out packaging technology is developing towards next-generation packaging technologies such as multi-chip, thin packaging and three-dimensional system integration.

[0003] However, there are still many problems to be solved in fan-out packaging technology, among which the reliability of multi-chip integrated rewiring is one of the problems. Specifically, due to the large difference in thermal ex...

Claims

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