A packaging method for improving the yield rate of foplp chip circuits

Abstract

The invention provides a packaging method for improving the circuit yield of an FOPLP chip. The packaging method comprises the steps: placing temporary bonding glue to a carrier plate; placing a metalframe on the carrier plate; pasting a functional chip on the temporary bonding glue; carrying out plastic package on the functional chip and the temporary bonding glue; performing grinding and thinning for 1 [mu]m - 1 mm, and performing flattening; pasting a dielectric layer, and performing laser trepanning on the dielectric layer to expose an I / O interface; manufacturing a metal seed layer; performing coating of a wet film; performing exposing and developing to manufacture a blind hole; performing copper deposition and thickening on the blind hole to manufacture an RDL layer; removing the wet film, carrying out flash etching to remove the redundant metal seed layer, carrying out ball mounting, and removing the carrier plate and the temporary bonding glue. According to the packaging method for improving the FOPLP chip circuit yield, the charge density of the metal surface during electroplating of the chip on the large-size carrier plate can be effectively improved, so that the packaging efficiency is improved, the quality of a chip metal circuit is improved, and better electrical performance is achieved.

Description

technical field [0001] The invention relates to the technical field of fan-out packaging, in particular to a packaging method for improving the circuit yield of FOPLP chips. Background technique [0002] The large board-level fan-out packaging structure is characterized by the simultaneous packaging of multiple chips on a large carrier board. Due to the large area of ​​the carrier board, it is significantly helpful to reduce production costs, but it also faces many challenges; it is difficult to use traditional packaging processes to make electroplating, Development, etching, deposition and other processes meet the process requirements, and metallization is a key factor affecting the electrical performance of the final chip. [0003] In the existing chip packaging technology, the metal circuit layer is generally produced by an electroplating process. During electroplating, the metal to be plated is used as the cathode, and the pre-plated metal cations are deposited on the me...

AI Technical Summary

Problems solved by technology

However, with the development of large-size board-level packaging technology, the area of ​​the substrate is getting larger and larger, and the charge density on the charged metal cannot meet the current density requirements on the chip during the manufacture of large-size substrate packaging.

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