A method, system, device and storage medium for FTL power-down testing

A technology of electrical testing and logic data, applied in static memory, instruments, etc., can solve problems such as the inability to measure FTL in the first time, the inability to verify NAND characteristics, and the impact of FTL power-down testing, so as to improve test accuracy and improve test performance. Efficiency, the effect of ensuring independence

Active Publication Date: 2021-05-04
广州匠芯创科技有限公司
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Problems solved by technology

Existing solutions lack pertinence. PC-side simulation tests cannot verify NAND characteristics in real power-off scenarios. In addition, product-level power-off tests cannot detect FTL problems in the first place due to the addition of file system verification functions. When FTL is powered off, it is prone to key data loss, which affects the power-off test of FTL

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  • A method, system, device and storage medium for FTL power-down testing
  • A method, system, device and storage medium for FTL power-down testing
  • A method, system, device and storage medium for FTL power-down testing

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Embodiment Construction

[0028] The idea, specific structure and technical effects of the present invention will be clearly and completely described below in conjunction with the embodiments and accompanying drawings, so as to fully understand the purpose, scheme and effect of the present invention.

[0029] It should be noted that, unless otherwise specified, when a feature is called "fixed" or "connected" to another feature, it can be directly fixed and connected to another feature, or indirectly fixed and connected to another feature. on a feature. In addition, descriptions such as up, down, left, and right used in the present disclosure are only relative to the mutual positional relationship of the components of the present disclosure in the drawings. As used in this disclosure, the singular forms "a", "the", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. Also, unless defined otherwise, all technical and scientific terms used herein have...

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Abstract

The present invention relates to an FTL power-down test method, system, device and storage medium. By dividing the FTL into a data overwriting area for writing logic data and an information recording area for writing characteristic data, the information is recorded The area is divided into two sub-areas, and the characteristic data, data address and data length generated each time are accumulated and alternately written into the two sub-intervals of the information recording area to play a backup role. In the two sub-intervals, select the sub-interval in which data was written last time, and use the characteristic data, data address and data length of the sub-interval as the verification data, so that only the data written during power-off is lost during the verification, effectively improving the Verify the integrity of data, improve the security of key data, and improve test efficiency.

Description

technical field [0001] The invention relates to the field of flash memory, in particular to an FTL power-down test method, system, device and storage medium. Background technique [0002] As a non-volatile storage device, NAND Flash is more and more widely used. Limited by its own physical characteristics and product application fields, the design of the NAND Flash algorithm needs to fully consider the power-down scenario. Electronic products using NAND Flash allow the page data being programmed to be lost when the power is turned off. However, if FTL continues to program the page after power-on next time, its data will not be guaranteed to be correct. Whether the NAND Flash FTL algorithm can correctly handle the page programmed during power-off will directly affect the data security of the product. [0003] The NAND Flash feature only supports continuous page programming, and each cell in the page can only be programmed once before the next erase. If a power failure occ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C29/18
CPCG11C29/18
Inventor 周坤
Owner 广州匠芯创科技有限公司
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