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Shield gate field effect transistor and manufacturing method thereof

A technology of field effect transistors and shielding gates, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., to achieve the effect of free adjustment of capacitance

Pending Publication Date: 2019-12-27
WILL SEMICON (SHANGHAI) CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The relationship between breakdown voltage and resistance at a specific N-type doping concentration is limited by the silicon limit (the law of mutual limitation between the breakdown voltage and on-resistance of the product)

Method used

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  • Shield gate field effect transistor and manufacturing method thereof
  • Shield gate field effect transistor and manufacturing method thereof
  • Shield gate field effect transistor and manufacturing method thereof

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Embodiment Construction

[0034] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiment of the application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiment of the application. Obviously, the described embodiment is only It is an embodiment of a part of the application, but not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the scope of protection of this application.

[0035] It should be noted that the terms "first" and "second" in the description and claims of the present application and the above drawings are used to distinguish similar objects, but not necessarily used to describe a specific sequence or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances such...

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Abstract

The invention discloses a method for forming a shield gate field effect transistor. The method comprises the following steps that: a first dielectric layer which is of a groove-shaped structure is deposited on the inner wall of a groove formed in a conductive epitaxial layer, the groove of the first dielectric layer is filled with a shielding gate, and back etching is performed on the shielding gate; back etching is performed on the first dielectric layer, so that the top of the first dielectric layer is flush with the top of the shield gate; the tops of the first dielectric layer and the shield gate are filled with a second dielectric layer until the second dielectric layer reaches a first target thickness, two sides of the second dielectric layer contact with the inner wall of the groove, and the second dielectric layer and the first dielectric layer are made of different materials; and a gate oxide layer is grown at the upper part of the second dielectric layer and on the inner wallof the groove, and then a gate is deposited, wherein the gate is located at the middle part of the gate oxide layer. With the method provided by the technical schemes disclosed by the invention adopted, required capacitance can be freely adjusted according to needs.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a shielded gate field effect transistor and a manufacturing method thereof. Background technique [0002] Shield gate (Shield gate) field effect transistor (MOSFET), referred to as SGT, is widely used in the field of medium and low voltage switching devices due to its low on-resistance. Well (P-well) and N-type doping (N-EPI) deplete each other, according to Poisson's equation, its electric field distribution is a triangular electric field. The relationship between breakdown voltage and resistance at a specific N-type doping concentration is limited by the silicon limit (the law that exists between the breakdown voltage and on-resistance of a product). A lateral electric field is formed by introducing a shielded gate structure (the structure is short-circuited with the source) in the original N-type doped epitaxial layer. Finally, the electric field distribution is chang...

Claims

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Application Information

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IPC IPC(8): H01L29/78H01L21/336H01L29/423
CPCH01L29/78H01L29/66477H01L29/4236
Inventor 衷世雄
Owner WILL SEMICON (SHANGHAI) CO LTD
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