Locality quantification-based parallel task allocation scheduling method for multi-core system

Abstract

The invention discloses a locality quantification-based parallel task allocation scheduling method for a multi-core system. Local parameter values of parallel tasks are considered in allocation and scheduling of the parallel tasks; the tasks to be executed are reasonably grouped through the local parameter values, so that the difference of the local parameter values among the groups is as small aspossible, it is guaranteed that the parallel tasks distributed to the same processor computing core have the minimum resource competition for the shared cache, and therefore the failure rate of the shared cache is effectively reduced. Meanwhile, the program memory access address sequence is sampled, and the local parameter values of the single task and the parallel task are calculated by utilizing the footprint value, so that the huge time expenditure of the traditional local quantitative analysis is remarkably reduced, and the task allocation and scheduling efficiency is improved. Accordingto the method, the utilization rate of the on-chip shared cache can be effectively improved, the execution performance of parallel tasks and the throughput rate of a multi-core system are improved, and the operability is good.

Description

technical field [0001] The invention belongs to the field of multi-core processor task scheduling, in particular to a multi-core system parallel task allocation and scheduling method based on locality quantization. Background technique [0002] With the rapid development of semiconductor technology, the size of transistors has entered the nanometer era, and the integration of chips has also been highly developed. More and more computing cores are packaged on a single chip. Multi-core architecture has also become the mainstream computer processor architecture today. In order to avoid expensive off-chip storage data access, reduce access delay, and improve cache (cache memory) utilization, computer processors adopt a hierarchical cache architecture. The highest-level L1 cache has the fastest operating speed and the smallest capacity at the same frequency as the CPU; while the lowest-level cache has the slowest operating speed (still much faster than off-chip storage) and the ...

AI Technical Summary

Problems solved by technology

However, this method is mainly applicable to thread-level parallel subtasks with shared data, and is not suitable for solving the problem of shared cache contention on multiprocessor systems

Images