Memory access system

Abstract

The invention discloses a memory access system, and belongs to the technical field of a computer architecture and processor microstructure design. The memory access system comprises a storage controller and a memory, wherein the memory is a 128-bit memory composed of two groups of storage particles, and each group of storage particles has 64 bits; the storage controller comprises a user interface,a first control path CCH0, a second control path CCH1, a first data path DCH0 and a second data path DCH1; the user interface is used for receiving an upper-layer memory access request and distributing the upper-layer memory access request to the first control path CCH0, the second control path CCH1, the first data path DCH0 and the second data path DCH1, and then is responsible for collecting response and returning; in the single-channel mode, the first control path CCH0 or the second control path CCH1 is used for managing the first data path DCH0 and the second data path DCH1 at the same time; and in the dual-channel mode, the first control path CCH0 and the second control path CCH1 manage the first data path DCH0 and the second data path DCH1 respectively. The memory access system canbe flexibly configured to support a high-reliability application scene and a high-bandwidth application scene.

Description

technical field [0001] The invention belongs to the technical field of computer architecture and processor microstructure design, and specifically relates to a memory access system. Background technique [0002] Storage controller is an important part of computer system. At present, the mainstream memory used in the field of high-performance computing is still the DDR (Double Data Rate) series memory, mainly the new generation of DDR4 memory. DDR series memories are usually spliced ​​into modules with a data bit width of 64 bits, such as UDIMM and RDIMM (if the parity is considered, it is 64+8=72 bits, unless otherwise specified, the subsequent bit width in this article only refers to the data bit width , not referring to the total bit width of the parity bit on the tape). The traditional 64-bit memory controller technology only controls one memory channel with a 64-bit data width, which is responsible for converting the upper-layer memory access request into a command tha...

AI Technical Summary

Problems solved by technology

Data verification requires stronger encoding, which requires greater data granularity. For example, ChipKill encoding that can correct errors in the entire particle requires a data granularity of 512+64 (512-bit data + 64-bit checksum). 64-bit memory controller can not do

On the other hand, in the field of high-performance computing, the data granularity available to the processor core is larger, such as issuing a memory access request of more than 128B, and if a 64-bit memory controller is used, multiple DDR4 accesses are required, which will lead to more large memory access latency

[0004] For this reason, conventional methods are difficult to achieve highly reliable data check coding

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