Resistive random access memory and preparation method thereof

Abstract

The invention provides a preparation method of a resistive random access memory. The preparation method comprises the following steps: providing a substrate; forming a lower electrode on the substrate; forming a first resistive random material layer on the lower electrode and the upper surface of the substrate; forming a second resistive random material layer on the first resistive random materiallayer, wherein the resistive state of the second resistive random material layer is different from that of the first resistive random material layer; and forming an upper electrode on the second resistive random material layer. The second resistive random material layer is additionally arranged between the first resistive random material layer and the upper electrode so that the conversion undervarious resistance states (>2) of the resistive random access memory can be realized, and thus multi-value memory can be realized and the data storage amount can be increased on the premise that the memory chip area is unchanged.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a resistive variable memory and a preparation method thereof. Background technique [0002] With the rapid development of modern information technology, people are constantly pursuing non-volatile memory chips with faster speed, higher capacity and lower power consumption to store massive data. The widespread use of smart phones and tablet computers and the promotion of cloud computing have put forward higher requirements on the performance and capacity of non-volatile memory chips. The current development trend of embedded non-volatile memory is large capacity, low power consumption, high density, high speed and low cost. [0003] With the further shrinking of the logic process, especially after entering the 40nm process node, it is more difficult to integrate traditional EEPROM or NORFLASH with the advanced logic process represented by HKMG and FinFET, and its high manufacturing ...

AI Technical Summary

Problems solved by technology

The structure of a common resistive variable memory: a substrate, a lower electrode (TiN) located on the substrate, a resistive material layer (TaOx) located on the lower electrode and the upper surface of the substrate, and a resistive material layer (TaOx) located on the upper surface of the resistive The upper electrode (TiN) above the variable material layer, this kind of resistive memory can generally only realize dual-value storage in high and low resistance states

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