A gaas pHEMT 2/3 dual-mode frequency division circuit

A circuit and mode division technology, applied in the field of GaAspHEMT2/3 dual-mode frequency division circuit, can solve the problems such as the inability to meet the requirements of ultra-high frequency circuits and the narrow operating frequency range of the circuit

Active Publication Date: 2021-09-10
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, the operating frequency range of this type of circuit is relatively narrow and relatively low, which cannot meet the requirements of ultra-high frequency circuits.

Method used

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  • A gaas pHEMT 2/3 dual-mode frequency division circuit
  • A gaas pHEMT 2/3 dual-mode frequency division circuit
  • A gaas pHEMT 2/3 dual-mode frequency division circuit

Examples

Experimental program
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Effect test

Embodiment 1

[0074] See figure 2 , figure 2 It is a schematic structural diagram of a GaAs pHEMT 2 / 3 dual-mode frequency division circuit provided by an embodiment of the present invention, including:

[0075] A frequency divider core circuit 1, connected to the logic gate circuit 2, for receiving a high-frequency differential signal, and outputting a level signal after frequency-dividing the high-frequency differential signal;

[0076] A logic gate circuit 2, connected to the frequency divider core circuit 1, for outputting a dual-mode frequency division signal after performing logic operations on the level signal;

[0077] Wherein, both the frequency divider core circuit 1 and the logic gate circuit 2 include a level conversion circuit.

[0078] See image 3 ,See figure 2 , figure 2 It is another structural schematic diagram of the GaAs pHEMT 2 / 3 dual-mode frequency division circuit provided by the embodiment of the present invention,

[0079] In this embodiment, the frequency ...

Embodiment 2

[0134] The effects of the present invention will be further described through simulation experiments below.

[0135] In this embodiment, the circuit diagram of the simulation experiment can be found in Figure 5 , including frequency divider core circuit, logic gate circuit, differential input sinusoidal signal CLK, CLKN and external DC bias voltage MC, MCN; differential input sinusoidal signal CLK, CLKN is connected to frequency divider core circuit, external DC bias voltage MC and MCN are connected to the logic gate circuit, and the differential output signal is connected to the output of the logic gate circuit. Using transient simulation, the amplitude of the two clock signals is 1V, the frequency is 6GHz, and the phase is 0° and 180°. MC and MCN are -1V, or -2V, V1=-1V, V2=-3V.

[0136] See Figure 7a~7b , Figure 7a~7b is the simulation result diagram provided by the embodiment of the present invention, where Figure 7a MC=-1V, MCN=-2V, at this time, the circuit reali...

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Abstract

The invention discloses a GaAs pHEMT 2 / 3 dual-mode frequency division circuit, comprising: a frequency divider core circuit (1), connected to the logic gate circuit (2), used to receive high-frequency differential signals, and The high-frequency differential signal is frequency-divided to output a level signal; the logic gate circuit (2) is connected to the frequency divider core circuit (1), and is used to output a dual-mode frequency division signal after performing a logic operation on the level signal; Wherein, both the frequency divider core circuit (1) and the logic gate circuit (2) include a level conversion circuit. The GaAs pHEMT 2 / 3 dual-mode frequency division circuit provided by the present invention uses the GaAs pHEMT process and adopts the source coupling structure (SCL) at the same time, so that the circuit can meet higher frequency requirements, and at the same time, the circuit can achieve higher operating speed , lower power consumption and lower noise.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a GaAs pHEMT 2 / 3 dual-mode frequency division circuit. Background technique [0002] As one of the important modules in high-frequency circuit design, the frequency divider is widely used in broadband communication systems. Frequency dividers are typically implemented using flip-flop circuits or latch circuits. As an important part of the phase-locked loop, the performance of the frequency divider largely determines the application range of the entire phase-locked loop. In order to meet the requirements of its high-frequency communication, it must be optimally designed. At present, high-speed frequency dividers generally use differential signals for transmission, and the working speed is high. In addition, the prescaler is divided by the power of two. Commonly used are single-mode, dual-mode and four-mode prescalers. However, when using a single-mode pr...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K23/00
CPCH03K23/00
Inventor 吕红亮赵冉冉乔世兴武岳张玉明
Owner XIDIAN UNIV
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