Double Data Rate Synchronous DRAM Data Strobe Calibration

Abstract

When calibrating the phase offset between the SDRAM data strobe ("DQS") signal and the data ("DQ") signal in the device, the data signal driver circuit impedance is adjusted to weaken when performing system-level memory testing Impedance matching on the DQ signal path. During memory testing, the phase shift is stepped through a range and an error count is determined for each test. The memory test can emulate the mission mode operation of the device. After memory testing, the optimal phase offset corresponding to the lowest error count is determined. In subsequent mission mode operation of the device, the DQS signal may be delayed with respect to the DQ signal by a value corresponding to the optimal phase offset.

Description

Background technique [0001] A computing device such as a desktop computer, laptop or tablet computer, smartphone, portable digital assistant, portable game console, etc., includes one or more processors (such as a central processing unit, graphics processing unit, digital signal processor, etc.) and one or more memories. To facilitate higher throughput, such memory may be of a type capable of high speed operation, such as double data rate synchronous dynamic random access memory ("DDR SDRAM"). [0002] Synchronous DRAM or SDRAM utilizes a source synchronous memory interface in which the data source ("DQ") signal during data transfers is relied upon to provide the data strobe ("DQS") signal used by the destination of the data transfer to (channel) to capture such data signals as they are transmitted to the target. In DDR SDRAM, the DQ signal is sampled (ie, latched) at the target by both rising and falling edges of the DQS signal. [0003] Dense routing of circuit routing ca...

AI Technical Summary

Problems solved by technology

While this technique can improve upon the straightforward techniques described above, effects such as crosstalk can cause data errors during mission mode operation

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