Semiconductor wafer test path planning method based on attention mechanism reinforcement learning

Abstract

The invention discloses a semiconductor wafer test path planning method based on attention mechanism reinforcement learning, which is used to solve the technical problem of poor versatility of the existing semiconductor wafer test path planning method. The technical solution is to use the deep reinforcement learning model architecture of the Soft Attention Mechanism to train the agent. In particular, the long-short-term memory architecture is adopted to make the state have memory ability, and the wafer size is gradually expanded by using the course learning method, and different probe card styles are trained by using transfer learning. The invention effectively overcomes the problem that the model is difficult to train when the wafer is enlarged, and is suitable for applications under various wafer sizes. By training the agent, the agent can test all the dies on the wafer with the least number of moving steps, which effectively reduces the number of probe moves and the moving distance, and has good versatility.

Description

technical field [0001] The invention relates to a semiconductor wafer test path planning method, in particular to a semiconductor wafer test path planning method based on attention mechanism reinforcement learning. Background technique [0002] Before packaging the semiconductor chip, the chip will be electrically tested with a probe card. The main purpose is to remove the defective chips on the wafer from subsequent packaging, so as to avoid the waste of packaging materials and subsequent equipment production capacity. For the unqualified grains in the first inspection, a second inspection will be carried out. At this time, these sparsely distributed grains need to be manually intervened, resulting in waste of labor costs and time. [0003] The document "Authorized Notification No. CN103344896B Chinese Invention Patent" proposes a test path selection method for semiconductor wafers. It first marks the positions of effective dies and invalid dies on the wafer map, repeatedl...

AI Technical Summary

Problems solved by technology

[0004] In order to overcome the shortcomings of poor versatility of existing semiconductor wafer test path planning methods, the present invention provides a semiconductor wafer test path planning method based on attention mechanism reinforcement learning

The invention effectively overcomes the problem that the model is difficult to train when the wafer is enlarged, and is suitable for applications under various wafer sizes

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