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Integrated circuit memory and forming method thereof

An integrated circuit and memory technology, applied in the field of integrated circuit memory and its formation, can solve problems such as substrate damage

Pending Publication Date: 2020-03-10
CHANGXIN MEMORY TECH INC
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  • Summary
  • Abstract
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  • Claims
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Problems solved by technology

[0004] Aiming at the problem that substrate damage is easily caused during the process of forming storage node contacts in the existing process, the present invention provides a method for forming an integrated circuit memory, in which epitaxial contact and conductive The storage node contact of the material layer can reduce or avoid substrate damage when removing the conductive material between adjacent storage node contacts

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  • Integrated circuit memory and forming method thereof
  • Integrated circuit memory and forming method thereof
  • Integrated circuit memory and forming method thereof

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Embodiment Construction

[0045] As introduced in the background technology, when forming an integrated circuit memory in the existing process, a storage node contact is formed on the substrate surface of the corresponding source / drain region to be electrically connected to the capacitor. However, due to the process of etching the polysilicon layer The etching selection of silicon is relatively low, and over-etching often causes damage to the substrate surface.

[0046] Figure 1(a) to Figure 1(d) It is a schematic cross-sectional view of a method for forming an integrated circuit memory during implementation. The following first combinesFigure 1(a) to Figure 1(d) The formation process of an integrated circuit memory is introduced.

[0047] FIG. 1( a ) is a schematic cross-sectional view of a method for forming an integrated circuit memory after bit lines are formed. Referring to FIG. 1( a ), a substrate 100 is provided with a plurality of active regions 110 and an isolation region 120 for defining th...

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Abstract

The invention relates to the field of integrated circuits, and provides an integrated circuit memory and a forming method thereof. In the forming method, an isolation layer is formed on the substrate,after openings exposing a plurality of second source / drain regions are formed in the isolation layer, and a plurality of corresponding epitaxial contacts are formed on the surface of the substrate corresponding to the plurality of second source / drain regions in the same opening by using an epitaxial growth process; a conductive material layer is then formed to cover the top surfaces of the plurality of epitaxial contacts and overlap the adjacent epitaxial contacts to form a cavity in the opening; and the conductive material layer is then etched to open the cavity and form a plurality of storage node contacts connected with the plurality of second source / drain regions in a one-to-one correspondence manner, and each storage node contact comprises epitaxial contacts which correspond to the second source / drain regions and are sequentially superposed along the direction far away from the surface of the substrate and a part of residual conductive material layer. The formation method is beneficial to removal of residues of conductive materials between adjacent storage nodes, shortens the etching time, and reduces or avoids damage to the substrate.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to an integrated circuit memory and a forming method thereof. Background technique [0002] In an integrated circuit memory in the prior art, such as a dynamic random access memory (Dynamic Random Access Memory, DRAM), each storage unit usually includes a capacitor and a transistor, wherein the capacitor is used for storing data, and the transistor is used for Controlling the access of the capacitor to data, the integrated circuit memory also includes a word line (word line) and a bit line (bit line) connected to each memory cell, specifically, the word line and the transistor The gate is connected, the bit line is connected to one source / drain region of the transistor, and the other source / drain region of the transistor is connected to the capacitor, so as to achieve the purpose of data storage and output. [0003] In the existing process, when forming the above capacitor, a pol...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/108H10B12/00
CPCH10B12/30H10B12/02
Inventor 不公告发明人
Owner CHANGXIN MEMORY TECH INC
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