Error calibration method and system for high-speed analog-to-digital converter

Abstract

The invention discloses an error calibration method and system for a high-speed analog-to-digital converter, and the method comprises the steps: adding a pseudo-random injection module into a first-stage MDAC structure of an ADC, changing a transfer function of the pseudo-random injection module, and obtaining three types of outputs: first-stage MDAC digital output, pseudo-random code injection module output, and ADC other module digital output; constructing a parallelogram height parameter function related to ADC sampling capacitor mismatch conditions by taking the obtained three types of outputs as signal input, and performing corresponding LMS algorithm iteration to obtain a converged capacitor mismatch error coefficient; constructing a gain statistical parameter function related to thegain error of the ADC operational amplifier, and performing corresponding LMS algorithm iteration to obtain a converged gain error coefficient; and correcting the final output of the ADC by adoptingthe obtained capacitance mismatch error coefficient and gain error coefficient. According to the invention, various dynamic performances of the high-speed ADC can be improved.

Description

technical field [0001] The invention belongs to the technical field of analog-to-digital converter chip design, in particular to an error calibration method and system for high-speed analog-to-digital converters. Background technique [0002] Under 5G high-speed communication applications, devices such as broadband transceivers and small mobile base stations require the support of high-performance analog-to-digital converter chips. Different from digital circuits, analog circuits have many non-ideal effects, especially in the chip structure of high-speed analog-to-digital converters, because of the limited amplifier gain error and capacitance mismatch error caused by process mismatch, the analog-to-digital conversion The performance of the device chip is seriously degraded. Taking a high-speed ADC (analog-to-digital converter) with 12Bit (bit) quantization precision and 100MSps (sampling per second) sampling rate as an example, under the condition of only 60dB amplifier gai...

AI Technical Summary

Problems solved by technology

At present, most of the existing calibration methods are foreground calibration, which needs to interrupt the normal working cycle of the ADC, which is not conducive to the rapid response of the electronic system

The existing background calibration can only calibrate one non-ideal error, and it is difficult to calibrate two or more non-ideal errors; or, it is necessary to use the redundant design of analog modules to meet the calibration requirements

Therefore, the existing calibration methods are difficult to improve the performance of the ADC

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