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Memory reliability simulation verification method and device and storage medium

A technology of simulation verification and memory, applied in the field of memory, can solve problems such as difficult coverage, difficult yield, large memory, etc., and achieve the effect of improving simulation speed and ensuring accuracy

Active Publication Date: 2020-03-20
芯创智(上海)微电子有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] With the advancement of integrated circuit technology, the area of ​​the memory unit is getting smaller and smaller, and the memory integrated on a single chip is getting bigger and bigger, which makes it more and more difficult to increase the yield
In order to design high-reliability memory, it needs to be simulated at various process corners, various voltages, and various temperatures, but this is still difficult to cover all combinations
The most reliable method is to perform Monte Carlo simulation, but if you perform 10,000 Monte Carlo simulations on the memory, the simulation time and machine computing power are not allowed.

Method used

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  • Memory reliability simulation verification method and device and storage medium
  • Memory reliability simulation verification method and device and storage medium
  • Memory reliability simulation verification method and device and storage medium

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0040] Such as figure 2 As shown, a simulation verification method for memory reliability, including:

[0041] S100. Based on local process deviation parameters, obtain threshold voltage deviation values ​​of transistors in each unit of the memory through a Monte Carlo simulation method. Each unit includes a memory unit, an amplifier unit connected to the memory unit, and a write circuit unit.

[0042] Specifically, under the condition that the local process deviation parameter Local sigma is configured as 1.0, the threshold voltage deviation value is obtained by performing 10,000 simulations on the transistor through the Monte Carlo method.

[0043] S200. Based on the global process deviation parameter and the threshold voltage deviation value of the transistor of each unit, respectively simulate the read data operation and write data operation of the memory under various process corners, and obtain simulation results.

[0044] craft corner Global process deviat...

Embodiment 2

[0071] Based on the first embodiment, the structure of the memory unit and the amplifier unit and the process of reading data through the amplifier unit will be described in detail below. The transistors described herein are all MOS transistors.

[0072] image 3 It is a configuration diagram for read deviation simulation, the upper part of the figure is the memory unit, and the lower part is the amplifier unit.

[0073] The memory unit is an SRAM memory storage unit, including: transistors T1-T6, wherein T1 and T2 are P-type transistors, T3 and T4 are N-type transistors, and they form an inverter. T5 and T6 are transmission tubes of the SRAM memory storage unit, which are N-type transistors; nodes NT and NC are also included, and NT stores 1 bit data. NT connects the drains of T2 and T5, the source of T4, the gates of T1 and T3, NC connects the sources of T6 and T1, the drain of T3, the gates of T2 and T4, and the source of T5 connects the bit line BL , The drain of T6 is ...

Embodiment 3

[0091] Based on the first embodiment, the structure of the memory unit and the writing circuit unit and the process of writing data through the writing circuit unit will be described in detail below.

[0092] Figure 4 It is a configuration diagram for writing deviation simulation, the upper part of the figure is the memory unit, and the lower part is the writing circuit unit.

[0093] The memory unit is an SRAM memory, including: transistors T1-T6, wherein T1 and T2 are P-type transistors, T3 and T4 are N-type transistors, and they form an inverter. T5 and T6 are transmission pipes, and also include nodes NT and NC, where NT stores 1 bit data. NT connects the drains of T2 and T5, the source of T4, the gates of T1 and T3, NC connects the sources of T6 and T1, the drain of T3, the gates of T2 and T4, and the source of T5 connects the bit line BL , The drain of T6 is connected to the bit line BLC, BLC is the inverse of BL, and NC stores the inverse of the data stored in NT, if N...

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Abstract

The invention discloses a memory reliability simulation verification method and device and a storage medium, and the method comprises the steps: S100, obtaining a threshold voltage deviation value ofa transistor of each unit of a memory through a Monte Carlo simulation method based on a local technological deviation parameter; S200, based on the global process deviation parameter and the threshold voltage deviation value of the transistor of each unit, respectively simulating the data reading operation and the data writing operation of the memory under various process corners to obtain a simulation result; and S300, when it is determined that the simulation result shows that the data reading operation and the data writing operation of the memory under various process corners are both in anormal state, determining that the memory has reliability. Monte Carlo simulation is adopted in a local range, the threshold voltage deviation value of each unit transistor of the memory is obtained,analogue simulation time substitution is carried out under various specific process angles in a global range, the reliability of the memory is verified, the simulation precision is guaranteed, and the simulation speed is increased.

Description

technical field [0001] The invention relates to the field of memory, in particular to a memory reliability simulation verification method, device and storage medium. Background technique [0002] With the progress of integrated circuit technology, the area of ​​the memory unit is getting smaller and smaller, and the memory integrated on a single chip is getting bigger and bigger, which makes it more and more difficult to improve the yield. In order to design high-reliability memory, it needs to be simulated at various process corners, various voltages, and various temperatures, but it is still difficult to cover all combinations. The most reliable method is to perform Monte Carlo simulation, but the simulation time and machine computing power are not allowed to perform tens of thousands of Monte Carlo simulations on the memory. Contents of the invention [0003] In view of the defects existing in the prior art, the object of the present invention is to provide a memory re...

Claims

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Application Information

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IPC IPC(8): G06F30/33
CPCY02D10/00
Inventor 吴汉明朱敏
Owner 芯创智(上海)微电子有限公司
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