A method of manufacturing a semiconductor

Abstract

The invention provides a semiconductor manufacturing method. After forming a patterned top wiring layer, a dielectric material is firstly filled to form a first dielectric layer covering the top wiring layer. The first dielectric layer is formed in the first dielectric layer. If there are air bubbles, then the first dielectric layer is planarized, and the air bubbles in it can be exposed after the planarization, so that the air bubbles can be reduced or even eliminated by filling the dielectric material again, and the filling quality of the dielectric layer can be improved , after planarization again, the flatness of the wafer surface can be guaranteed, and then the yield rate of the bonding process of the wafer can be improved. In this method, it is not necessary to increase the thickness of the dielectric material to avoid the occurrence of air bubbles and affect the flatness of the wafer, and improve the flatness of the wafer. The stability of the subsequent process and reduce the manufacturing cost.

Description

technical field [0001] The invention relates to the field of semiconductor devices and their manufacture, in particular to a semiconductor manufacturing method. Background technique [0002] With the continuous development of semiconductor technology, wafer-level packaging technology has been widely used, which is to use the wafer-level packaging technology to stack and bond different wafers together. [0003] In the hybrid bonding technology, after the top wiring layer is formed on the wafer, bonding pads are formed in the dielectric layer, and the bonding pads and dielectric layer are used to bond with another wafer, while the flatness of the wafer surface It is extremely critical to the bonding process. In the application where the top wiring layer is aluminum, the flatness of the wafer surface before bonding is achieved through the planarization process, and the dielectric layer is formed after filling the top wiring layer of aluminum, and bubbles are easily formed betw...

AI Technical Summary

Problems solved by technology

In the application where the top wiring layer is aluminum, the flatness of the wafer surface before bonding is achieved through the planarization process, and the dielectric layer is formed after filling the top wiring layer of aluminum, and bubbles are easily formed between the aluminum wiring, which is flat The chemical process needs to avoid the exposure of bubbles, so as not to affect the performance of the device, which requires the dielectric layer to be thick enough, resulting in increased process time and increased process volatility

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