Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

A device and method for accurately diagnosing cbit array faults in batches

An open circuit fault, array technology, applied in the direction of measuring devices, measuring electricity, measuring electrical variables, etc.

Active Publication Date: 2021-11-02
SHANGHAI NCATEST TECH CO LTD
View PDF0 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0018] The purpose of the present invention is to provide a method for accurately diagnosing cBit array faults in batches of ATE equipment, which can solve the problem of cBit connectivity in large batches of ATE testing equipment, that is, it can effectively diagnose connectors during manufacturing and equipment maintenance. Connector problems caused by various processes, welding and human factors when cBit is led out

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A device and method for accurately diagnosing cbit array faults in batches
  • A device and method for accurately diagnosing cbit array faults in batches
  • A device and method for accurately diagnosing cbit array faults in batches

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0118] In an embodiment of the present invention, step S21 may be performed for the diagnosis of a small number of non-adjacent power supply pin VCC channel resources in the cBit array.

[0119] Step S21: For the first type of pin channel resources, the level of the power supply pin VCC does not change, and the level output of all 0 -> all 1 -> all 0 is output by changing the level of its surrounding channels, that is, the level pulse matrix method is used to Diagnose failure of power supply pin VCC channel resource.

[0120] The specific diagnostic result is reflected in step S31, that is, for the first type of pin channel resources, the read value of the unit in the read register corresponding to the VCC channel of the power supply pin is always 1, indicating that the channel is normal; the corresponding position of the VCC channel of the power supply pin The read value is always 0, which means the channel is normally low or an open circuit fault; the read value of the corre...

Embodiment 2

[0129] In the embodiment of the present invention, for the fourth type of pin channel resources, output all 0 -> all 1 -> all 0 diagnosis, specifically include the following steps:

[0130] Step S51: Control all the fourth-type pin channel resources to output all 0s, and obtain and judge whether all 0s are obtained from the data reading control CPLD; control all the fourth-type pin channel resources to output all 1s, and read the data from the control CPLD Obtain and determine whether all 1s are present; control all fourth-type pin channel resources to output all 0s, and obtain and determine whether all 0s are obtained from the data reading control CPLD. The effect of outputting all 0 is as follows

[0131] Table 3 shows:

[0132] Col1 Col2 Col3 Col4 Col5 Col6 Col7 Col8 Col9 Col10 Col11 Col12 Col13 ROW1 0 0 0 0 0 0 0 0 0 0 0 0 0 ROW2 0 0 0 0 0 0 0 0 0 0 0 0 0 ROW3 0 0 0 0 0 0 VCC 0 0 0 0 ...

Embodiment 3

[0138] In the embodiment of the present invention, step S23 can be executed for fault diagnosis such as a short circuit of the fourth type of pin channel resource, which specifically includes the following steps:

[0139] Step S231: Set Row=1, Col=1 to 1, and other positions to 0; the result is as follows

[0140] Table 5 shows:

[0141] Col1 Col2 Col3 Col4 Col5 Col6 Col7 Col8 Col9 Col10 Col11 Col12 Col13 ROW1 1 0 0 0 0 0 0 0 0 0 0 0 0 ROW2 0 0 0 0 0 0 0 0 0 0 0 0 0 ROW3 0 0 0 0 0 0 VCC 0 0 0 0 0 0 ROW4 0 0 0 0 0 0 0 0 0 0 0 0 0 ROW5 0 0 0 0 0 0 0 0 0 0 0 0 0 ROW6 0 0 0 GND 0 0 0 0 0 0 0 0 0 ROW7 0 0 0 0 0 0 0 0 NC 0 0 0 0 ROW8 0 0 0 0 0 0 0 0 0 0 0 0 0 ROW9 0 0 0 0 0 0 0 0 0 0 0 0 0 ROW10 0 0 0 0 0 0 0 0 0 0 0 0 0 ROW11 0 0 0 0 0 0 0 0 0 0 0 0 ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A device and method for accurately diagnosing cBit array faults in batches, the device includes a cBit resource board, a diagnostic PB board and a CPU processing unit; the cBit resource board includes the first cBit array on the cBit resource board, M*N write registers and output Control CPLD; Diagnosis PB board includes the second cBit array, M*N read register and data reading control CPLD; CPU processing unit is connected with cBit resource board and diagnosis PB board respectively; The present invention constructs the output pin of cBit resource connector (Pin foot) on the potential island to diagnose whether there is a connection fault on the pin, not only can effectively perform accurate and effective fault diagnosis on the connectivity of a large number of cBit resource connectors, but also accurately diagnose the location of the cBit resource connector The fault point and fault type of the Pin.

Description

technical field [0001] The present invention relates to the field of semiconductor automatic test equipment (Automatic Test Equipment, ATE for short), in particular to a device and method for accurately diagnosing faults of cBit arrays in batches. Background technique [0002] cBit can be understood as Control Bit. In the process of testing the chip, automatic test equipment (ATE) provides customers with delay (Relay) switching function and multi-channel (Mux) routing function by outputting high and low levels. [0003] In high-end ATE equipment, due to the large number of devices under test (DUT for short) that need to be tested in parallel, the amount of various resources required is very large. From the perspective of cBit resources, there may be thousands of pins. [0004] see figure 1 , figure 1 Shown is a schematic diagram of a single cBit simple circuit in the prior art. see figure 2 , figure 2 Shown is a functional schematic diagram of a single cBit channel in...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/26G01R31/28
CPCG01R31/2601G01R31/2834
Inventor 吕吉强
Owner SHANGHAI NCATEST TECH CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com