Method of inspecting dual graph manufacturing constraints

A dual graphic and graphic technology, applied in constraint-based CAD, special data processing applications, instruments, etc., to reduce the probability of occurrence, ensure correctness, and facilitate the display of error positions

Active Publication Date: 2020-04-03
北京华大九天科技股份有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] Chip designers and foundry personnel can only find problems based on visual inspection or during the manufacturing stage

Method used

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  • Method of inspecting dual graph manufacturing constraints
  • Method of inspecting dual graph manufacturing constraints
  • Method of inspecting dual graph manufacturing constraints

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Embodiment Construction

[0080] The preferred embodiments of the present invention will be described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described here are only used to illustrate and explain the present invention, and are not intended to limit the present invention.

[0081] figure 1 It is a flow chart of a method for checking dual graphics manufacturing constraints according to the present invention, which will be referred to below figure 1 , a method for checking dual pattern manufacturing constraints of the present invention is described in detail.

[0082] First, in step 101, an adjacency matrix graph model is established. In this step, the Voronoi diagram is established first, and then the final connection diagram is established based on the Voronoi diagram and according to the horizontal and vertical constraints. A Voronoi diagram only needs to be built once.

[0083] Preferably, the user needs to pre-determine the hor...

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Abstract

The invention discloses a method for inspecting dual graph manufacturing constraints. The method comprises the following steps: 1) establishing an adjacent matrix graph model for a graph; 2) defininga path constraint requirement of the graph; 3) defining the parity of the graph; 4) based on the parity of the graph and the path constraint requirement, performing path traversal on the adjacent matrix graph model; and 5) summarizing and classifying the graphs violating the path constraint requirements. According to the method for checking the dual graph manufacturing constraints, the probabilityof the double graph manufacturing constraints can be effectively reduced, so that the correctness of standard unit design is ensured.

Description

technical field [0001] The invention relates to the technical field of EDA design, in particular to a method for checking double pattern manufacturing constraints. Background technique [0002] With the continuous development of integrated circuits and continuous updating of process technology, there are more and more constraints on chip manufacturing. The CM0B layer is a layer in the chip that cuts the metal layer. Under the most advanced 5nm process technology, the CM0B layer adopts double patterning technology during the manufacturing process. In this process, the graphics have different mask properties (mask), so double graphics manufacturing constraints need to be met, otherwise chip manufacturing will fail and cause huge losses. [0003] The dual graphics manufacturing constraint means that the total number of graphics that form a ring due to satisfying the distance constraint must be an even number. Standard units are arranged in rows, and the graphics that make up...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/398G06F111/04
CPCY02P90/30
Inventor 马坤周汉斌傅静静陈彬
Owner 北京华大九天科技股份有限公司
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