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Optimization device and method of controlling optimization device

An optimization device and circuit technology, applied in the field of optimization devices and control optimization devices, can solve problems such as large-scale optimization devices that are difficult for multiple computing processing units

Active Publication Date: 2020-04-14
FUJITSU LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, in general, it is difficult to realize a large-scale optimized device using multiple arithmetic processing units

Method used

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  • Optimization device and method of controlling optimization device
  • Optimization device and method of controlling optimization device
  • Optimization device and method of controlling optimization device

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Experimental program
Comparison scheme
Effect test

no. 1 approach

[0031] figure 1 A view showing an example of the optimization device according to the first embodiment.

[0032] The optimization device 10 according to the first embodiment includes four stages of arithmetic processing units 11 , 12 , 13 and 14 which are connected to each other in a ring and search for a ground state of an Ising model. The number of stages of the operation processing unit is not limited to four, but may be M, that is, an integer of 2 or greater. Each of the arithmetic processing units 11 to 14 is, for example, a one-chip semiconductor integrated circuit (eg, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), etc.). Furthermore, for example, the arithmetic processing units 11 to 14 may be provided in a one-chip semiconductor integrated circuit.

[0033]In the optimization device 10, since the updating process of the state of the Ising model is repeated many times, it is desirable that the arithmetic processing units 11...

no. 2 approach

[0070] image 3 is a view showing an example of the optimization device according to the second embodiment.

[0071] The optimization device 30 according to the second embodiment includes: a control device 31; a storage device 32; M-level cores 33a1, 33a2, . . . and 33aM; a shared bus 34;

[0072] The control means 31 controls the cores 33a1 to 33aM. The control device 31 is a processor including an arithmetic circuit that executes program instructions, such as a central processing unit (CPU) or a digital signal processor (DSP). The control device 31 executes programs stored in the storage device 32 . The control device 31 may include a plurality of processors or a plurality of processor cores, and control of the cores 33a1 to 33aM may be performed in parallel using the plurality of processors or processor cores.

[0073] The storage device 32 stores information on the Ising model and the like. The storage device 32 can store programs to be executed by the control device 3...

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Abstract

The invention relates to an optimization device and a method of controlling an optimization device. The optimization device includes M-level arithmetic processing circuits connected in a ring. Each level of arithmetic processing circuits includes: a determination circuit that determines whether update is allowed for each first bit based on the information of the Ising model; a first selection circuit for selecting an update candidate bit from update permission bits that are allowed to be updated based on the determination circuit result and outputting its identification information; a countingcircuit which counts the number of update permission bits; a status update circuit which updates the value of any second bit based on the identification information provided by the last level operation processing circuit to the foremost level. In addition to the foremost level operation processing circuit, each level of the operation processing circuit includes a second selection circuit, the second selection circuit selects the first identification information output by the first selection circuit by the first probability obtained by dividing the number of update permission bits by the sum of the number provided by the previous level operation processing circuit, and selects the second identification information provided by the previous level operation processing circuit by the second probability obtained by subtracting the first probability from 1.

Description

technical field [0001] Embodiments described herein relate to optimization devices and methods of controlling the same. Background technique [0002] In the related art, there is a method of calculating a multivariate optimization problem in which a Neumann-type computer is ineffective by using an optimization device (also called an Ising machine or a Boltzmann machine) of an Ising-type energy function. The optimization means replaces the problem to be calculated with an Ising model representing the spin behavior of the magnetic substance, and calculates the problem. [0003] The optimizer can model this problem using, for example, a neural network. In this case, each of the plurality of bits corresponding to all the spins included in the Ising model serves as a neuron that is based on the value of another bit and indicates the value of its own bit and the other bit. A weighting factor (also called coupling factor) of the magnitude of the interaction between bits outputs 0...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06N3/063G06N3/08
CPCG06N3/063G06N3/08G06N10/00G06N5/01G06N3/047G06N3/044G06N3/045G06F17/11G06F7/57G06F7/58
Inventor 米冈升
Owner FUJITSU LTD