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Reliability verification method and system based on analog-to-digital converter

A technology of analog-to-digital converter and verification method, applied in analog/digital conversion, analog/digital conversion calibration/test, code conversion, etc., can solve the problem of ADC positioning time-consuming, inability to distinguish ADC analog unit and digital part, indistinguishable Problems such as the logic link from the chip to the host computer, to achieve the effect of shortening the time and verifying the circuit is simple and effective

Active Publication Date: 2020-04-17
3PEAK INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] In the prior art, the logic digital unit usually does not do DFT (Design For Test, design for testability). When the ADC is abnormal, it is impossible to distinguish the problem of the ADC analog unit and the digital part, and it is also impossible to distinguish the entire logic link from the chip to the host computer. problem, there is a greater reliability risk, and when the ADC is abnormal, it takes a long time to locate the problem

Method used

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  • Reliability verification method and system based on analog-to-digital converter
  • Reliability verification method and system based on analog-to-digital converter
  • Reliability verification method and system based on analog-to-digital converter

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Embodiment 1

[0059] ginseng Figure 4 Shown is a module schematic diagram of the reliability verification system based on the analog-to-digital converter in this embodiment, wherein the digital-to-analog converter ADC includes an analog unit 10 and a logic digital unit 20, and the data path inside the logic digital unit 20 is a series of D Flip-flops, of course, D flip-flops also include other combinatorial logic, etc., which will not be described in detail in the present invention.

[0060] The test signal providing unit in this embodiment is a pattern generator 30, and the test signal provided by the pattern generator 30 is a 0 / 1 code, and the reliability verification of the logic digital unit 20 is realized through the test signal.

[0061] In addition, a gate 40 is provided in this embodiment. The input terminals of the gate 40 are respectively connected to the analog unit 10 and the pattern generator 30 , and the output terminals are connected to the logic digital unit 20 .

[0062] ...

Embodiment 2

[0073] Different from Embodiment 1, Embodiment 1 realizes the logic judgment by extracting the quiescent current IDDQ of the logic digital unit 20, while in this embodiment, the logic of the logic digital unit is judged by the output signal of the logic digital unit, and the reliability The modules of the verification system are exactly the same as those in Embodiment 1, and will not be repeated here.

[0074] In this embodiment, the reliability verification method based on the analog-to-digital converter specifically includes the following steps:

[0075] S1. Provide a test signal and send it to the logic digital unit in the analog-to-digital converter.

[0076] Code pattern (Pattern) generator 30 outputs test signal after receiving CONVST signal, and strobe selects the output signal of pattern generator as the input signal of logic digital unit 20 under the reliability verification state, and then injects to logic digital unit 20 0 / 1 yard.

[0077] S2. Extracting the outpu...

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Abstract

The invention discloses a reliability verification method and system based on an analog-to-digital converter. The method comprises the following steps of: S1, providing a test signal and sending the test signal to a logic digital unit in the analog-to-digital converter, S2, extracting a quiescent current and / or an output signal of the logic digital unit, and S3, judging whether the logic in the logic digital unit is normal or not according to the quiescent currents and / or the output signals in different clock periods. The reliability verification mechanism is introduced for the logic digital unit of the ADC, the verification circuit is simple and effective, and the reliability verification of the logic digital unit can be realized by testing the quiescent current IDDQ and / or comparing theoutput code pattern.

Description

technical field [0001] The invention belongs to the technical field of analog-to-digital conversion, and in particular relates to a reliability verification method and system based on an analog-to-digital converter. Background technique [0002] ginseng figure 1 As shown, an analog-to-digital converter (Analog to Digital Converter, ADC) usually includes an analog unit and a logic digital unit (Logic), the logic digital unit (Logic) receives the output signal of the comparator Comparator in the analog unit, and CLK is the output signal of the logic digital unit clock signal. [0003] In the prior art, the logic digital unit usually does not do DFT (Design For Test, design for testability). When the ADC is abnormal, it is impossible to distinguish the problem of the ADC analog unit and the digital part, and it is also impossible to distinguish the entire logic link from the chip to the host computer. There is a large reliability risk, and it takes a long time to locate the p...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/10
CPCH03M1/1071Y02D10/00
Inventor 程龙
Owner 3PEAK INC