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Bit manipulation capable direct memory access

A technology of memory access and bit manipulation, applied in instrumentation, computing, electrical and digital data processing, etc., can solve the problem that the processor thread cannot perform other tasks, etc.

Pending Publication Date: 2020-04-21
MICROCHIP TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

During this operation, the processor or a processor thread assigned to the task may not be able to perform other tasks

Method used

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  • Bit manipulation capable direct memory access
  • Bit manipulation capable direct memory access
  • Bit manipulation capable direct memory access

Examples

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Embodiment Construction

[0015] figure 1 is an illustration of a system 100 for bit manipulation in DMA according to an embodiment of the disclosure. System 100 may be implemented in any suitable environment, such as a microcontroller, system-on-chip (SoC), computer, tablet, smartphone, server, printer, router, industrial automation controller, automotive electronic system, or any other suitable electronic equipment. System 100 may include a DMA controller 104 configured to transfer memory from a data space 102 to another data space 106 .

[0016] DMA controller 104 may be implemented by analog circuits, digital circuits, or any suitable combination thereof. DMA controller 104 may include a data buffer 110 . Additionally, the DMA controller may include a bit manipulation mask circuit 114 .

[0017] Data space 102 and data space 106 may include any suitable type of memory or other elements for storing data in system 100 . For example, data space 102 may include a series of memory locations in spec...

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Abstract

A memory management circuit includes a direct memory access (DMA) channel. The DMA channel includes logic configured to receive a buffer of data to be written using DMA. The DMA channel further includes logic to perform bit manipulation in real-time during a DMA write cycle of the first buffer of data.

Description

[0001] Related Patent Applications [0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 576,966, filed October 25, 2017, the contents of which are hereby incorporated in their entirety. technical field [0003] The present disclosure relates to memory access, and more particularly to bit-operable direct memory access (DMA). Background technique [0004] For memory transfer operations between different memories or memory components, the processor can use programming input and output instructions to read, write and set data. However, execution of such instructions by the processor may be slow due to the latency of memory accesses. Access to memory may require physical interfacing with mechanical or electronic components of the memory. The instruction executed by the processor does not end until the read or write is complete. So the processor is waiting for the end of the instruction which, as mentioned above, may execute slowly due to memo...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/28
CPCG06F13/28G06F13/1673G06F2213/2806G06F9/30134G06F13/4018
Inventor Y·元永斯戈S·鲍林C·范伊登I·沃杰沃达N·拉贾
Owner MICROCHIP TECH INC