PCIE exchange chip port configuration system and method

Abstract

The invention discloses a PCIE (Peripheral Component Interconnect Express) exchange chip port configuration system and method. The comprises an exchange chip kernel, a plurality of ports and an EEPROM (Electrically Erasable Programmable Read-Only Memory) controller interface; the exchange chip kernel further comprises a crossbar switch and a configuration module; the crossbar switch is used for forwarding a transaction layer packet passing through the PCIE exchange chip; the configuration module is used for configuring the port, configuring the port as an upstream port or a downstream port, and controlling the opportunity of establishing a link for each port link; the upstream port receives configuration from an upstream link and configuration of the configuration module, and performs read or write operation on a port configuration register unit in the upstream port; and the downstream port receives the configuration information from the configuration module and performs reading or writing operation on the port configuration register unit in the downstream port. According to the system and method, the port configuration can be quickly completed, and the time limit requirement of aPCIE protocol on PCIE chip initialization is met.

Description

technical field [0001] The present invention relates to the technical field of high-speed interconnection bus (Peripheral Component Interconnect Express, PCIE) of computer peripheral equipment, in particular to a PCIE switch chip port configuration system and method. Background technique [0002] The PCIE bus is based on the traditional PCI system, retains some excellent features of the traditional PCI bus, and is compatible with the PCI bus in terms of software configuration. The PCIE bus changes the parallel bus structure of PCI to serial to break through the speed bottleneck, and at the same time uses point-to-point connections, CRC checks, etc. to ensure high real-time and high reliability of the data bus. A high-performance, general-purpose I / O interconnect bus defined for a variety of computing and communication platforms. The PCIE bus is currently widely used in computing systems such as workstations and servers, as well as embedded computing and communication platfo...

AI Technical Summary

Problems solved by technology

Although there are many PCIE switch chips on the market, it is difficult to find literature on the specific implementation mechanism of the PCIE switch chip port configuration. This patent proposes a PCIE switch chip port configuration implementation mechanism, which can quickly realize the port configuration of the PCIE switch chip. , to meet the PCIE protocol's time limit requirements for PCIE chip initialization

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