Semiconductor device and preparation method thereof

Abstract

The invention discloses a preparation method of a semiconductor device. The preparation method comprises the following steps: providing a first substrate and a second substrate, wherein the first substrate is provided with a first bonding interconnection surface, and the second substrate is provided with a second bonding interconnection surface; preparing a single crystal laminated structure on the first substrate, wherein the single crystal laminated structure comprises a plurality of heterogeneous material layers and second substrate layers which are alternately stacked; preparing a plurality of nanowires or sheets on the first substrate; forming a gate dielectric layer and a gate on the plurality of nanowires or sheets; forming a metal contact; forming a plurality of layers of interconnection structures on the formed structure; and sequentially forming a metal liner and a passivation layer on the plurality of layers of interconnection structures. The channel material formed by the preparation method does not have lattice imperfection, can avoid influencing the performance and reliability of a subsequently formed device, and does not limit the forming process of a subsequent structure; and the preparation method has good applicability. The invention also provides a semiconductor device.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof. Background technique [0002] As the feature size of integrated circuits continues to shrink, especially at nodes below 5nm, traditional triple-gate or double-gate Fin Field-Effect Transistor (Fin Field-Effect Transistor, abbreviated as FinFET) devices cannot continue to shrink due to their own structural problems. To solve this problem, a Gate-All-Around (Gate-All-Around, abbreviated as GAA) structure can be used. The GAA structure can adjust the size of stacked nanowire or sheet gate-around devices to ensure that the gate can be on the top and sides of the channel, but also below the channel. [0003] Channels in existing stacked nanowires or sheet-ring-gate devices are generally formed by epitaxy using an STI first process, or are realized by periodically forming Si / SiGe stacks by using an STI last process. [0...

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Problems solved by technology

[0004] However, the formation methods of the above two channels are likely to cause lattice defects in the formed channel, which affects the performance and reliability of the final semiconductor device.

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