31results about How to "Avoid Lattice Defects" patented technology

The invention relates to semiconductor technology, aims to overcome the difficulty of manufacturing a semiconductor power device with a trench / gate super-junction, and provides a method for manufacturing a longitudinal power semiconductor device. The technical scheme of the invention is as follows: firstly a first semiconductor region is formed by epitaxial process; a first oxide layer and a deposited mask layer are formed at the top of the first semiconductor region, the photoetching operation is performed, a first trench is formed by etching, a second oxide layer is formed on the two side walls of the first trench, the second oxide layer is removed by wet-etching, a third oxide layer is formed on the inner wall of the trench, a second semiconductor region is formed on the two side walls of the first trench, the third oxide layer is removed, a fourth oxide layer is formed, insulation dielectrics are packed and then planarization is carried out, a body region is formed, a second trench is formed on the body region by etching, a trench gate is made, and finally a source region and a body contact region are formed, followed by electrode preparation and surface passivation. The method has the benefits of having low process difficulty and being applied to MOS-controlled longitudinal devices.

The invention relates to a method for preparing high saturation magnetisation CoFe alloy powder by using hydrotalcite as a single precursor, which belongs to the technical field of a metal soft magnetThe invention relates to a method for preparing high saturation magnetisation CoFe alloy powder by using hydrotalcite as a single precursor, which belongs to the technical field of a metal soft magnetic material. The CoFe alloy powder can be prepared by calcining hydrotalcite precursor with the general chemical formula of Co1-bFeb(OH)2R<n->b / n.nH2O for 3 to 6 hours under the condition of 673-1073Kic material. The CoFe alloy powder can be prepared by calcining hydrotalcite precursor with the general chemical formula of Co1-bFeb(OH)2R<n->b / n.nH2O for 3 to 6 hours under the condition of 673-1073K in the environment with the ratio of H2 to N2 being 4-8 percent, wherein b in the Co1-bFeb(OH)2R<n->b / n.nH2O is b is more than or equal to 0.25 and is less than or equal to 0.5. Compared with the priin the environment with the ratio of H2 to N2 being 4-8 percent, wherein b in the Co1-bFeb(OH)2R<n->b / n.nH2O is b is more than or equal to 0.25 and is less than or equal to 0.5. Compared with the prior art, the invention has the advantages that the prepared CoFe alloy powder does not need to be ground in a ball milling mode, has the grain diameter of 20-150 nanometers, and accurate chemical propoor art, the invention has the advantages that the prepared CoFe alloy powder does not need to be ground in a ball milling mode, has the grain diameter of 20-150 nanometers, and accurate chemical proportion and complete grain structure, avoids the diversification of metal sources and lattice defect caused by powerful grinding and has superior magnetic property.rtion and complete grain structure, avoids the diversification of metal sources and lattice defect caused by powerful grinding and has superior magnetic property.

The invention relates to a high-frequency horizontal double diffusion oxide semiconductor device and a manufacturing method thereof. The method comprises the steps that a pad oxide layer with a first preset thickness is generated on the upper surface of an epitaxial layer; a sinking area is defined in a first default area on the pad oxide layer and a groove with a preset depth is formed in the pad oxide layer in the sinking area; the bottom part of the groove is located in the oxide layer; sinking area ion implantation is carried out in the groove to form the sinking area; and silicon nitride is deposited on the upper surface of the pad oxide layer and then an active region is defined by employing the groove as an alignment mark and is prepared. The relatively thick oxide layer is formed on the epitaxial layer, the groove is formed in the oxide layer through etching, and the groove is taken as the alignment mark of forming a sinking layer, so that a fault is prevented from being formed in an ion implantation area in a traditional technology; the on resistance of the device is reduced; and the lattice defect is avoided.

The invention discloses a deposition and doping device for the absorbing layer of a thin film solar cell, which includes a deposition chamber, a first supply mechanism, a second supply mechanism and an evaporation heating mechanism. The source material transported in the chamber, the deposition heating element used to heat the source material into the source material vapor is arranged on the deposition chamber, the second supply mechanism transports the dopant material to the evaporation heating mechanism to be heated into the dopant material vapor, and the dopant material vapor The vapor pipe is transported into the deposition chamber, and the vapor pipe is provided with a third switch, and the source material vapor and the dopant material vapor are output from the deposition chamber to be deposited on the substrate. The present invention integrates deposition and doping, can carry out deposition of source materials, and can also carry out diffusion doping. distribution, to ensure that the absorbing layer of thin film solar cells has good and stable performance.

The invention relates to a preparation method of an electrode material for a supercapacitor and the electrode material prepared by the method, which comprises the following steps: (a) drying the crop straw at 100-150°C to remove moisture, and then placing it under airtight conditions to raise the temperature Calcining at 200-350°C for 0.5-5 hours to obtain a pre-carbonized product; (b) taking the pre-carbonized product and adding it to a mixed solution of ferric chloride and sodium chloride, soaking it for 10-20 hours, and drying it at 80-150°C , then placed in an inert gas atmosphere and calcined at 700-1500°C for 1-5 hours, and naturally cooled to obtain a carbonized product. The concentration of the ferric chloride is 5-10g / 100ml, and the concentration of the sodium chloride is 10-20g / 100 m; (c) Wash the carbonized product several times with dilute hydrochloric acid with a concentration of 0.5-2 mol / L, filter the filter residue, rinse the filter residue several times with deionized water, and dry it. Fe3+ can form a stable complex with the oxygen-containing functional groups on the surface of the pre-carbonized product, avoiding the formation of a large number of lattice defects in the calcined carbon material, and is conducive to the construction of a 3D microporous structure.

The invention discloses a radio-frequency horizontal double diffusion metal oxide semiconductor device and a manufacturing method thereof. An alignment mark of a subsidence region is formed by employing a pad oxide layer etching method, so as to define an active region. The method is simple in process, the maneuverability is high, and meanwhile, the condition that a fracture surface exists in an injection region due to a groove formed through silicon etching in the prior art is avoided, so that the injection region can be better connected with the subsidence region; and the on resistance of the device is effectively reduced. Furthermore, due to the absence of silicon etching, the lattice defect easily generated in silicon etching is also avoided.

The invention discloses a method for preparing a semiconductor device, which includes the following steps: providing a first substrate and a second substrate; wherein, the first substrate has a first bonding interconnection surface, and the second substrate has a second bond A single crystal stack structure is prepared on the first substrate; wherein the single crystal stack structure includes several alternately stacked heterogeneous material layers and a second substrate layer; several nanowires are prepared on the first substrate or sheet; form a gate dielectric layer and a gate on several nanowires or sheets; form metal contacts; form several layers of interconnection structures on the formed structure; sequentially form metal pads and passivation on several layers of interconnection structures Floor. The channel material formed by the preparation method does not have lattice defects, can avoid affecting the performance and reliability of subsequent devices, and does not limit the formation process of subsequent structures; it has good applicability. The invention also provides a semiconductor device.

A semiconductor structure and a forming method thereof are provided. The forming method comprises a substrate; a stack structure is formed on the surface of the substrate in order and comprises a plurality of sacrificial layers and a plurality of first semiconductor layers, the surface of the substrate is a sacrificial layer, and the sacrificial layers and the first semiconductor layers are stacked alternately; the stack structure is etched to form a groove in the surface of the substrate and a first semiconductor line and a sacrificial line on two sides of the groove; the sacrificial line is removed so that the first semiconductor line is suspended above the substrate; the first semiconductor line is subjected to annealing processing, so that the cross section of the first semiconductor line is round; an epitaxial technique is used to form a second semiconductor layer of the surface of the first semiconductor line, and the carrier mobility of the second semiconductor layer is greater than that of the first semiconductor nano line. The method can improve the performance of a fully surrounded gate field effect transistor formed on the first semiconductor nano line.

The invention relates to a ZnO / CdTe / CdS nanometer cable array electrode used for a solar battery and a preparation method thereof. The ZnO / CdTe / CdS nanometer cable array electrode is composed of an ITO conductive glass substrate, a ZnO buffering thin layer, a ZnO nanometer line array layer, a CdTe nanometer cable layer and a CdS nanometer crystal protective layer which are arranged from inside to outside; and the saturation photocurrent density of the ZnO / CdTe / CdS nanometer cable array electrode is improved to 12.4 mA / cm<2> through a CdS and CdTe sensitization technology. The ZnO / CdTe / CdS nanometer cable array electrode provided by the invention has the advantages of simple and practicable preparation process, low cost, high productive rate and good market application prospect.

The invention discloses a manufacturing method for a groove type semiconductor power device, relating to the technical field of the semiconductor power device. The manufacturing method comprises the following key technology steps of: growing and filling a groove by etching the groove and adopting an anisotropy epitaxy technology to form a second semiconductor region, locally etching at the top of the second semiconductor region to form a narrow high-concentration n or p column, filling an insulating medium and flattening, and afterwards, forming a body region by adopting laterally epitaxial overgrowth and the like. The manufacturing method has the advantages that the negative influences of the filling and planarization of the groove and the manufacturing and planarization of a groove gate on the formed body region, a body contact region and a source region are avoided; the bottom of the groove gate is flush with the lower interface of the body region or lower than the lower interface of the body region, thereby increasing the withstand voltage of the device; a complex mask is not needed, and the influence of a small-angle injection technology on a channel region is avoided; super junctions formed by adopting a multiple-time epitaxial injection manner and lattice defects caused by the super junctions are avoided; and the on-resistance is greatly reduced.

The invention provides a semiconductor device structure and a manufacturing method thereof. The semiconductor device structure comprises a semiconductor substrate, a plurality of insulating layers, a plurality of metal wiring layers, conductive plugs in a device region and conductive plugs in a virtual region, wherein the semiconductor substrate is divided into the device region and the virtual region; the virtual region is arranged on the edge of the semiconductor substrate; one insulating layer is arranged on the semiconductor substrate; the metal wiring layers are formed among the insulating layers; the conductive plugs in the device region are arranged in each insulating layer and penetrate through the insulating layer in the thickness direction, and are used for connecting the metal wiring layers; and the conductive plugs in the virtual region are arranged in one insulating layer and penetrate through the insulating layer in the thickness direction, and are used for directly connecting any metal wiring layer with the semiconductor substrate. The invention has the following advantage: the electric charges accumulated in the metal wiring layers and the insulating layers during etching are timely released, thus avoiding lattice defects and device damage caused by residual electric charges.

The invention discloses a method for reducing e-SiGe lattice imperfections in the PMOS manufacturing process. The method includes the steps of etching and cleaning the shape and the appearance of a silicon base of a silicon wafer, conducting pre-cleaning before extension growth, placing the silicon wafer into an etching chamber of an extension growth machine table, conducting dry etching on the silicon wafer so as to remove a natural oxidation layer, placing the silicon wafer into an extension process chamber, and conducting the SiGe extension growth process on the silicon wafer. Through in-situ etching on the natural oxidation layer, generated before the silicon wafer enters the extension growth machine table, of the silicon wafer, the lattice imperfections which are caused to the extension process and the subsequent process by the natural oxidation layer are avoided, and therefore device failures are reduced, and the yield of the silicon wafer is improved; meanwhile, rework in the process production is reduced, the production cycle of the product is shortened, and production cost of the product is reduced.