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A kind of semiconductor device and its preparation method

A semiconductor and device technology, applied in the field of semiconductor devices and their preparation, can solve problems affecting the performance and reliability of semiconductor devices, channel lattice defects, etc.

Active Publication Date: 2021-09-14
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, the formation methods of the above two channels are likely to cause lattice defects in the formed channel, which affects the performance and reliability of the final semiconductor device.

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  • A kind of semiconductor device and its preparation method
  • A kind of semiconductor device and its preparation method
  • A kind of semiconductor device and its preparation method

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Embodiment Construction

[0064] The specific implementation manners according to the present invention will be described below in conjunction with the accompanying drawings.

[0065] In the following description, many specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways different from those described here, therefore, the present invention is not limited to the specific embodiments disclosed below limit.

[0066] As the feature size of integrated circuits continues to shrink, especially to nodes below 5nm, traditional tri-gate or double-gate FinFET devices cannot continue to shrink due to their own structural problems. To solve this problem, the GAA structure can be used. Specifically, the GAA structure can adjust the size of stacked nanowires or sheet gate-around devices to ensure that the gate can be on the top and sides of the channel, but also below the channel.

[0067] The channels in the existing stac...

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Abstract

The invention discloses a method for preparing a semiconductor device, which includes the following steps: providing a first substrate and a second substrate; wherein, the first substrate has a first bonding interconnection surface, and the second substrate has a second bond A single crystal stack structure is prepared on the first substrate; wherein the single crystal stack structure includes several alternately stacked heterogeneous material layers and a second substrate layer; several nanowires are prepared on the first substrate or sheet; form a gate dielectric layer and a gate on several nanowires or sheets; form metal contacts; form several layers of interconnection structures on the formed structure; sequentially form metal pads and passivation on several layers of interconnection structures Floor. The channel material formed by the preparation method does not have lattice defects, can avoid affecting the performance and reliability of subsequent devices, and does not limit the formation process of subsequent structures; it has good applicability. The invention also provides a semiconductor device.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof. Background technique [0002] As the feature size of integrated circuits continues to shrink, especially at nodes below 5nm, traditional triple-gate or double-gate Fin Field-Effect Transistor (Fin Field-Effect Transistor, abbreviated as FinFET) devices cannot continue to shrink due to their own structural problems. To solve this problem, a Gate-All-Around (Gate-All-Around, abbreviated as GAA) structure can be used. The GAA structure can adjust the size of stacked nanowire or sheet gate-around devices to ensure that the gate can be on the top and sides of the channel, but also below the channel. [0003] Channels in existing stacked nanowires or sheet-ring-gate devices are generally formed by epitaxy using an STI first process, or are realized by periodically forming Si / SiGe stacks by using an STI last process. [0...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/06H01L21/336H01L29/78
CPCH01L29/0669H01L29/0673H01L29/66795H01L29/785
Inventor 殷华湘张青竹徐忍忍
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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