Method for reducing e-SiGe lattice imperfections in PMOS manufacturing process

Abstract

The invention discloses a method for reducing e-SiGe lattice imperfections in the PMOS manufacturing process. The method includes the steps of etching and cleaning the shape and the appearance of a silicon base of a silicon wafer, conducting pre-cleaning before extension growth, placing the silicon wafer into an etching chamber of an extension growth machine table, conducting dry etching on the silicon wafer so as to remove a natural oxidation layer, placing the silicon wafer into an extension process chamber, and conducting the SiGe extension growth process on the silicon wafer. Through in-situ etching on the natural oxidation layer, generated before the silicon wafer enters the extension growth machine table, of the silicon wafer, the lattice imperfections which are caused to the extension process and the subsequent process by the natural oxidation layer are avoided, and therefore device failures are reduced, and the yield of the silicon wafer is improved; meanwhile, rework in the process production is reduced, the production cycle of the product is shortened, and production cost of the product is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuit manufacturing technology, in particular to a method for reducing e-SiGe (embedded silicon germanium) lattice defects in a PMOS manufacturing technology. Background technique [0002] Today, semiconductor integrated circuit technology is advancing very rapidly. According to Moore's Law, the feature size of integrated circuits will decrease by 30% every 18 months, while the integration level will double. In the advanced CMOS (Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor) integrated circuit process, the traditional method of reducing the thickness of the gate oxide layer can no longer meet the needs of the device. Therefore, people have to use other methods to improve device performance, such as high dielectric constant gate oxide technology and stress enhancement technology. [0003] The most important thing in the stress enhancement meth...

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Problems solved by technology

[0012] Therefore, how to provide a method for reducing e-SiGe lattice defects in the PMOS manufacturing process, avoiding the lattice defects caused by the epitaxy and subsequent processes caused by the formation of a natural oxide layer before the silicon wafer is put into the epitaxy machine, and solving the existing problems at the same time Problems with processes that need to be reworked

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