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Rapid implementation method of Turbo codes

An implementation method and fast technology, applied in the field of communication, can solve the problems of difficult hardware implementation and low calculation amount, and achieve the effect of simple hardware implementation, good scalability, and convenient calling

Pending Publication Date: 2020-05-08
10TH RES INST OF CETC
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AI Technical Summary

Problems solved by technology

[0013] The purpose of the present invention is to solve the problem that Turbo coding hardware is difficult to realize, to provide a simple structure, easy to expand, simple hardware implementation, strong practicability, low calculation amount, fast implementation method of Turbo coding based on FPGA, the above-mentioned method of the present invention The purpose can be achieved through the following technical solutions

Method used

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  • Rapid implementation method of Turbo codes
  • Rapid implementation method of Turbo codes
  • Rapid implementation method of Turbo codes

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Embodiment Construction

[0023] refer to figure 1 . According to the present invention, based on FPGA, utilize MATLAB algorithm mathematical tool software, generate the used interleave relation of the second pass encoding, be used for timing control and the delay device of two-way encoding data alignment, component encoder, specific code rate Turbo code encoding output Puncher, input FIFO for register clearing, output FIFO for timing control and output data adjustment, parallel to serial converter, and interleaver and ROM table for interleaving component encoder encoding. When interleaving, the binary sequence x to be encoded is sequentially written into a pseudo dual-port RAM; and the read address is provided by the corresponding ROM table of the interleaver. According to the address provided by the interleaving ROM table, the information in the RAM is read once to complete the interleaving, and the interleaving sequence X2 is obtained. The input data information of the codeword sequence of the bin...

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Abstract

The invention discloses a rapid implementation method of Turbo coding, and aims to provide a Turbo coding implementation method which is simple in hardware implementation, high in practicability and low in operation amount. The method is implemented by the following technical scheme: during data interleaving, binary sequence input information data to be coded is written into a pseudo dual-port RAM, and the data is read according to an interleaving relationship stored in an ROM table to finish interleaving; to-be-coded code word sequence input data information is divided into two paths, one path of input information X1 is input into a component coder 1 to obtain an output sequence O1, the other path of input information is interleaved through an interleaver, an obtained information sequenceX2 is input into a component coder 2 for coding, and a sequence O2 is output; and the output sequences O1 and O2 of the two component coders are sent to a puncher for code rate adjustment, and the puncher performs punching coding according to the required code rate and multiplexes the output sequences O1 and O2 with the original information sequence output OO to generate code word output. The method can be compatible with different interleaving relationships.

Description

technical field [0001] The invention belongs to the communication field, and further relates to a channel coding technology, which can be used in a turbo code decoder of a next-generation broadband wireless communication system, especially a method for quickly realizing channel coding based on an FPGA-based turbo code. Background technique [0002] Channel coding is an important part of the communication system and an important means to improve the reliability of the communication system. Its performance directly affects the quality of communication. Because Turbo codes well apply the random coding and decoding conditions in Shannon's channel coding theorem, thus obtaining a decoding performance that is almost close to the limit of Shannon's theory, Shannon uses the channel coding theorem to illustrate the existence of good codes that approach channel capacity, but does not No practical method for constructing "good codes" is given. In practice, when the error probability o...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/29H03M13/27H04L1/00
CPCH03M13/2972H03M13/2975H03M13/2732H03M13/2739H03M13/2771H04L1/0002
Inventor 朱胜利罗宁王宇舟张庭兰谢玲
Owner 10TH RES INST OF CETC
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