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Power grid voltage rapid phase locking method with high robustness

A technology with grid voltage and strong robustness, applied in the direction of single-grid parallel feeding arrangement, etc., can solve the problem of inability to achieve accurate and fast phase locking, achieve accurate and reliable phase locking process, facilitate popularization and application, and achieve simple effects

Pending Publication Date: 2020-05-15
CHONGQING UNIV
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  • Claims
  • Application Information

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Problems solved by technology

[0008] In view of this, the purpose of the present invention is to provide a fast grid voltage phase-locking method with strong robustness, so as to solve the problem that the existing genlocking technology cannot The Problem of Realizing Accurate and Fast Phase Locking

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  • Power grid voltage rapid phase locking method with high robustness
  • Power grid voltage rapid phase locking method with high robustness
  • Power grid voltage rapid phase locking method with high robustness

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Embodiment Construction

[0044] In order to further understand the content of the present invention, the present invention will be described in detail in conjunction with the accompanying drawings and embodiments.

[0045] Specifically, in a power system, a three-phase voltage signal containing DC components, harmonics, and unbalance can be expressed as:

[0046]

[0047] where v a , v b , v c Respectively a, b, c three-phase voltage signals, n is the harmonic order of the fundamental frequency (when n is a negative number, it means negative sequence harmonics), V aDC , V bDC , V cDC Respectively, the DC component amplitudes in the abc three-phase voltage, V n is the amplitude of the AC component in the three-phase abc, ω s is the fundamental angular frequency of the voltage signal, is the initial phase angle of the voltage signal.

[0048] Aiming at the three-phase voltage under the above-mentioned non-ideal working conditions of the power grid, the fast phase-locking method of the grid vol...

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Abstract

The invention discloses a power grid voltage rapid phase locking method with high robustness. A Clarke conversion unit, an orthogonal signal generator and a positive sequence calculation unit are used, positive sequence fundamental wave extraction under the working conditions that the power grid voltage signal contains direct current bias, imbalance and waveform distortion is realized, and then the three-phase power grid voltage is converted into a synchronously rotating direct current quantity through the Park conversion unit, and finally closed-loop control is realized through a sliding modecontroller, a correction unit and an integration unit, so that rapid extraction of the phase angle of the power grid voltage is completed. According to the method provided by the invention, various interferences contained in the three-phase power grid voltage can be eliminated in the whole phase locking process, and rapid and accurate phase locking is realized.

Description

technical field [0001] The invention relates to the technical fields of renewable energy and distributed power generation, in particular to a method for synchronous phase-locking of a grid-connected inverter. Background technique [0002] With the increasing demand for electricity, clean and renewable energy sources such as solar energy and wind energy are developing rapidly. The requirements for the stability and reliability of renewable energy grid-connected are getting higher and higher, and the stability control of the grid-side converter depends on the grid voltage synchronization strategy. How to ensure that the genlock method can quickly and accurately obtain the phase and amplitude of the positive-sequence fundamental voltage of the power grid is a key issue for realizing the integration of renewable energy into the grid. [0003] Nowadays, in a three-phase system, the most commonly used one is a Synchronous Reference Frame Phase Locked Loop (SRF-PLL). The basic pr...

Claims

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Application Information

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IPC IPC(8): H02J3/40
CPCH02J3/40
Inventor 陈家伟程云川侯帅丞
Owner CHONGQING UNIV
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