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Preparation method of three-dimensional memory and three-dimensional memory

A memory, three-dimensional technology, applied in the direction of semiconductor devices, electrical solid devices, electrical components, etc., can solve the problems of affecting the electrical performance of the bottom selection gate and the reduction of the production yield of the three-dimensional memory, so as to improve the production yield and avoid electrical performance. The effect of ensuring the doping concentration

Active Publication Date: 2021-05-28
YANGTZE MEMORY TECH CO LTD
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Problems solved by technology

[0003] The application provides a method for preparing a three-dimensional memory and a three-dimensional memory, which solves the problem that the laterally grown epitaxial structure affects the electrical properties of the bottom selection gate, so that the production yield of the three-dimensional memory is reduced.

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  • Preparation method of three-dimensional memory and three-dimensional memory
  • Preparation method of three-dimensional memory and three-dimensional memory
  • Preparation method of three-dimensional memory and three-dimensional memory

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[0042] The following will clearly and completely describe the technical solutions in the embodiments of the application with reference to the drawings in the embodiments of the application. Apparently, the described embodiments are only some of the embodiments of the application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of this application.

[0043] Growing the epitaxial structure on the side of the channel hole is a lateral growth method of the epitaxial structure, which is different from directly growing the epitaxial structure inside the channel hole. The epitaxial structure grown on the side of the channel hole can well avoid the epitaxial structure epitaxy. A series of problems caused by the damage of the epitaxial structure and the difference in the growth density and height due to the process conditions during the growth, ...

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Abstract

The present application provides a method for preparing a three-dimensional memory and a three-dimensional memory. The preparation method includes: providing a semiconductor structure, wherein the semiconductor structure includes a substrate, an epitaxial layer disposed on the substrate, and an epitaxial layer disposed on the epitaxial layer. A stacked structure on the layer, the semiconductor structure also has a gate spacer penetrating through the stack structure, and the gate spacer exposes the epitaxial layer; the first step is performed on the epitaxial layer through the gate spacer doped to form a doped epitaxial layer. The preparation method of the three-dimensional memory of the present application solves the problem that the laterally grown epitaxial structure affects the electrical performance of the bottom selection gate, so that the production yield of the three-dimensional memory is reduced.

Description

technical field [0001] The present application relates to the field of semiconductor technology, in particular to a method for preparing a three-dimensional memory and the three-dimensional memory. Background technique [0002] Three-dimensional memory is a memory that realizes the storage and transmission of data in three-dimensional space and greatly improves the storage capacity of storage devices. The epitaxial structure of the existing three-dimensional memory adopts the lateral growth method, which well avoids the related problems caused by the subsequent process, but the epitaxial structure of the lateral growth is limited by the existing process method, which will affect the electrical performance of the bottom selection gate and reduce the three-dimensional memory. Memory manufacturing yield. Contents of the invention [0003] The present application provides a method for preparing a three-dimensional memory and the three-dimensional memory, which solves the prob...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/11524H01L27/11529H01L27/11548H01L27/1157H01L27/11573H01L27/11575H10B41/35H10B41/27H10B41/41H10B41/50H10B43/27H10B43/35H10B43/40H10B43/50
CPCH10B41/35H10B41/27H10B43/35H10B43/27
Inventor 刘小欣薛磊
Owner YANGTZE MEMORY TECH CO LTD
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