40results about How to "Avoid electrical influence" patented technology

A radar/infrared compatible invisible coating resistant to 600 DEG C is disclosed. The invisible coating is on the surface of a metal substrate, and includes an adhesive layer, a 8YSZ-Al2O3 ceramic bottom layer, a high-temperature resistance coating, a 8YSZ isolating layer and a high-temperature conductor coating in order from bottom to top form the surface of the metal substrate. The high-temperature resistance coating and the high-temperature conductor coating are in paster forms, and pasters are arranged periodically. A preparing method of the invisible coating is also disclosed. The structure of the invisible coating has a radar/infrared compatible stealth function. A resistance type periodic structure is introduced so that the invisible coating has a good wave absorbing function, anda defect that traditional wave absorbing coatings need absorbents so as to cause unsatisfied wave absorbing performance, big influences on processes and instable performance is solved. A conductor periodic structure is introduced to the surface layer, and the radar/infrared compatible stealth function is achieved by utilizing a high reflectivity characteristic for the infrared waveband and a hightransmittance characteristic for the radar waveband.

The invention discloses an interface pressure distribution testing sensing element. The interface pressure distribution testing sensing element comprises a sensing film, electrodes uniformly arranged around the sensing film at intervals, a lead connected with the electrodes and an upper and lower insulating paint layer. The sensing film is made from a conductive polymer composite material provided with a piezo-resistive sensitivity characteristic, and the electrodes and the lead are used for outputting resistivity information of the sensing film in different positions. When in testing, the lead is connected with a testing instrument, the electrical impedance imaging technology is used for acquiring, testing and computing so as to obtain the resistivity distribution of the sensing film in different positions, and then the pressure distribution can be obtained through the relationship between the sensing film pressure and the resistivity. The interface pressure distribution testing sensing element can be used for measuring the interface pressure distribution and change, and has the advantages of simple structure, ultra-thin film, strong flexibility, high resolution and precision, large measuring range and low cost.

The invention discloses a manufacturing method for a double-face illuminated crystalline silicon solar cell. The method comprises the following steps of: (1) washing a raw silicon chip, and removing a damaged layer from the back face of the raw silicon chip; (2) performing single-face boron diffusion on the front face of the silicon chip in a back-to-back way, wherein the back face of the silicon chip is a diffusing face; (3) depositing a mask layer on the back face of the diffused silicon chip; (4) washing the front face of the silicon chip, removing a damaged layer, performing texturing, and removing a diffraction diffusion layer; (5) performing single-face phosphorus diffusion on the back face of the silicon chip in a back-to-back way, wherein the front face of the silicon chip is the diffused face; (6) removing a peripheral joint, impurity glass and a mask which are formed by the diffusion; (7) depositing an anti-reflection coating on each of the two faces of the silicon chip; and (8) printing a metal electrode on each of the two faces of the silicon chip, and performing sintering to obtain the double-face illuminated crystalline silicon solar cell. The influence of diffraction on the electrical properties of the cell is avoided, and the photoelectric efficiency of the cell can be improved by 0.3 to 0.5 percent; and the method has positive practical significance.

The invention relates to synthesis technology of nano cable, and in particular provides a preparation method for synthesizing the nano cable structure of the amorphous silica-coated single-walled carbon nano tube by an arc discharge method. The preparation method comprises the following steps: adopting a cathode and anode DC arc discharge mode to realize in-situ preparation; the anode is a consumptive anode formed by pressing graphite, silicon powder, catalyst and growth promoter; after arc starting discharge, carrying out coevaporation of raw materials including the graphite, the silicon powder, the catalyst and the growth promoter; and completing in-situ synthesis of the nano cable structure of one or more silica-coated single-walled carbon nano tubes. Silica has the characteristics of good thermal stability, high dielectric constant, small drain current and high compressive strength, and the like. and is an ideal material of insulation layers used in nano devices such as the nano cable and a field effect transistor; in addition, a core body of the developed nano cable consists of one or more single-walled carbon nano tubes, which is favorable for bringing into playing the nano size effect of the single-walled carbon nano tube and improving the performances such as efficiency and sensitivity of a fabricated nano device.

The invention provides a manufacturing method of an MOS (metal oxide semiconductor) device. The manufacturing method comprises the following steps of: providing a semiconductor substrate and forming a hard mask layer on the surface of the semiconductor substrate; etching the hard mask layer and the semiconductor substrate to form a first groove, wherein the bottom surface of the first groove is lower than the surface of the semiconductor substrate, and the height difference exists between the two; forming a gate dielectric layer on the surface of the semiconductor substrate at the bottom of the first groove; filling the first groove to form a gate electrode; removing the hard mask layer; and forming a thin film oxidation layer on the surface of the semiconductor substrate through a heat oxidation process, wherein the bottom surface of the thin film oxidation layer is higher than or flush with that of the gate dielectric layer. According to the manufacturing method disclosed by the invention, the bottom of the gate electrode is lower than the surface of the semiconductor substrate, and the height difference exists between the two; and when the thin film oxidation layer is formed by heat oxidation, the thickness loss of the semiconductor substrate is not greater than the height difference, so that a spacing interval between the bottom of the gate electrode and a channel is further eliminated and a silicon recess can be further prevented from affecting the electrical properties of the MOS device.

Provided is an electronic package comprising a carrier structure, an electronic element and a shielding member disposed on the carrier structure, an encapsulating layer formed on the carrier structurefor encapsulating the electronic element and the shielding member, a metallic layer formed on the encapsulating layer and electrically connected to the shielding member, and an alignment member disposed at a side of the encapsulating layer, thereby allowing the periphery of the electronic element to be covered by the shielding member and the metallic layer to avoid external electromagnetic interference.

The invention discloses a turnable-heating-tube mounting structure and an electric oven and aims to solve the problem that the side walls, on which a heating tube is arranged, of the inner container of a conventional electric oven are hard to clean. The turnable-heating-tube mounting structure comprises a box body and a heating tube mounted in the box body, wherein the box body is provided with a wall surface; the heating tube is mounted close to the wall surface and arranged in the box body in turnable manner; and in the turning state, at least part of the heating tube deviates from the wall surface. The invention also provides the electric oven with the mounting structure. The two ends of the heating tube are rotatably mounted on two side walls of the inner container of the electric oven, and the heating tube can rotate by a preset angle along the axis where the two end parts of the heating tube are positioned, so that the wall surface, on which the heating tube is fixed, of the inner container is exposed outside to be conveniently cleaned.

The embodiment of the invention discloses a thin film transistor and a preparation method thereof. The preparation method of the thin film transistor comprises a step of performing mulching treatmenton a back channel of a thin film transistor by utilizing O2 after photoresist is finally removed. The preparation method disclosed by the embodiment of the invention comprises the step of performing the mulching treatment on the back channel of the thin film transistor by utilizing O2 after the photoresist is finally removed, not only good photoresist removal effect can be achieved, but also influence on electrical properties of the back channel of the thin film transistor is also avoided, and product performance is improved.

The invention provides a common-type radar antenna cover and a winding forming method and relates to the field of radar antennas. The radar antenna cover comprises an isolation medium, a glass fiberglass cloth tape, a waterproof film and a glass fiber winding tow, wherein an antenna array is coated with the isolation medium, the glass fiberglass cloth tape, the waterproof film and the glass fiberwinding tow from inside to outside in sequence. The radar antenna cover is characterized in that the effect of integrating the radar antenna cover with the antenna array in a common type is achieved.By means of the structure, not only is the structural strength of the thin-walled antenna cover ensured but also the rigidity and wind resistance of the antenna array are enhanced, and the electricalperformance of the antenna array can be ensured.

The invention provides a method for low-pressure sintering a hybrid power module by nano-silver solder paste. The method can simultaneously sinter two chips with a large area difference and can obtaina solder paste layer having a high strength (>=30 MPa). The method comprises four processes including pre-drying, pressurizing, sintering, and reducing. The pre-drying process is to provide a certainviscosity for the solder paste to avoid the overflow of the excessive solder paste during the pressurizing process of a large-area chip. The pressurization process is to pressurize the large-area Sichip to promote the sintering, and not to pressurize the small-area SiC chip to avoid damage. The sintering process is carried out under a 50% air + 50% nitrogen atmosphere to ensure sufficient oxygen for the sintering of the solder paste and to avoid the oxide formation on the substrate surface. The reducing process is to reduce the surface oxide of the substrate by formic acid to remove copperoxide formed on the surface. The overall process flow of the invention is relatively simple, and is suitable for the manufacture of a hybrid power module having a large chip area difference.

The embodiment of the invention provides a display substrate and a display device and relates to the technical field of organic electroluminescence displayers. The display substrate solves the problem that in the prior art, electrical property drift is generated due to changes of the threshold voltage in a thin film transistor when an organic electroluminescence displayer is manufactured, avoids the influence on electrical properties of the thin film transistor, improves the stability of performance of products and reduces production cost. The display substrate comprises the thin film transistor and is characterized by further comprising a grounding circuit, wherein one end of the grounding circuit is connected to the thin film transistor, and the other end of the grounding circuit is grounded; the grounding circuit and a conducting layer structure of the thin film transistor are formed simultaneously in the process of manufacturing the thin film transistor. The display substrate and the display device are applied to manufacturing of the organic electroluminescence displayers.

The invention discloses a resistive memory and a manufacture method thereof. The method comprises: first of all, sequentially forming a first electrode, a variable resistance layer and a mask layer on a substrate; then, forming a dielectric layer covering the first electrode, the variable resistance layer and the mask layer on the substrate; next, performing an etching process to form an opening in the dielectric layer and the mask layer, the opening exposing a part of the variable resistance layer; afterwards, forming a second electrode in the opening, and afterwards, forming a conductive layer on the second electrode.

The invention provides a novel power supply power module structure with output protection and belongs to the field of semiconductor components. The novel power supply power module structure comprisesfour rectifier chips, an overvoltage protection chip, two input terminals, two output terminals and a plastic package body, and is characterized by further comprising a first frame unit, a second frame unit and a third frame unit which are arranged relatively in sequence; the four rectifier chips are arranged between the first frame unit and the second frame unit; the overvoltage protection chip is arranged between the second frame unit and the third frame unit to form a laminated structure; the two input terminals are led out of the first frame unit; the two output terminals are led out of the second frame unit; the four rectifier chips and the overvoltage protection chip are packaged integrally by the laminated structure, and a structure with the four rectifier chips laid flatly and integrated vertically with the overvoltage protection chip is formed, spatial arrangement of the package structure is more reasonable, the product occupies small planar space on a PCB, and the problem about space utilization rate of the PCB is solved.

The invention discloses a solar cell anaerobic annealing process. The solar cell anaerobic annealing process comprises the following steps of A. putting a cell into an annealing furnace; B. raising internal temperature of a furnace tube of the annealing furnace to a first temperature, and vacuumizing to a first pressure; C. keeping the first temperature and the first pressure; D. lowering internaltemperature of the furnace tube of the annealing furnace to a second temperature; E. raising pressure in the furnace tube of the annealing furnace to normal pressure; and F. discharging.