Fan-out type wafer level packaging structure and manufacturing method thereof

Abstract

The invention provides a fan-out type wafer level packaging structure and a manufacturing method thereof, and the method comprises the steps: providing a support wafer layer, and forming an adhesive layer on the support wafer layer; bonding a plurality of bare chipsto the surface of the adhesive layer, the bare chipshaving pins facing the adhesive layer surface; forming a pre-cured layer on the adhesive layer and sides, far away from the support wafer layer, of the bare chips, wherein the pre-cured layer covers the bare chips; forming a curing layer on one side, far away from the support waferlayer, of the pre-curedlayer; removing the support wafer layer and the adhesive layer to expose pins of the bare chips; forming a rewiring layer on the surfaces of one sides of the exposed pins of the bare chips, and forming spherical pins on the rewiring layer; polishing the cured layer to a predetermined thickness; cutting to form a fan-out type wafer level packaging structure; wherein the curedlayer and the pre-curedlayer have different thermal expansion coefficients, and the curedlayer and the bare chips have the same thermal expansion coefficient. The packaging structure produced by themethod reduces warping of the wafer in a fan-out wafer level packaging process.

Description

technical field [0001] The invention relates to the field of semiconductor chip packaging, in particular to a fan-out wafer-level packaging structure and a manufacturing method thereof. Background technique [0002] In the development process of the dynamic random access memory (DRAM, Dynamic Random Access Memory) manufacturing process, in the related art, the DRAM packaging structure 100 (such as Figure 1A shown) for packaging, including a die 101 , a plastic encapsulation layer 102 and pins 103 . For the opening 110 , the design of the position of the pad on the die 101 has strict requirements, and needs to match the manufacturing capability of the substrate factory. In addition, the WBGA DRAM packaging structure needs to transmit signals through the substrate, and there are strict requirements on the thickness of the DRAM packaging structure and the metal wiring lines in the substrate. [0003] The fan-out wafer-level packaging structure in the related art (such as Fi...

AI Technical Summary

Problems solved by technology

Due to the large difference in thermal expansion coefficient between the plastic sealing layer and the die, the overall structure is prone to warping after the plastic sealing layer is formed, which increases the difficulty of forming the redistribution layer and the ball pin process

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