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Device and system for shard creation

A destination, processor circuit technology for optimal dynamic shard creation to address issues such as low random read and write speeds

Pending Publication Date: 2020-06-23
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Compute-intensive IO-intensive graphics workloads suffer from high IO latency due to their random IO access patterns, as even fast non-volatile memory express (NVME) devices suffer from Much slower random read and write speeds than their sequential access speeds

Method used

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  • Device and system for shard creation
  • Device and system for shard creation
  • Device and system for shard creation

Examples

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Embodiment Construction

[0063] Various exemplary embodiments will be explained more fully hereinafter with reference to the accompanying drawings, in which some exemplary embodiments are shown. However, the presently disclosed subject matter may be embodied in many different forms and should not be construed as limited to only the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosed subject matter to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity.

[0064] It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, that element or layer A layer may be directly on, directly connected to, or directly coupled to, the other element or layer, or intervening elements or layers may be present. In contrast, when an...

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Abstract

According to one general aspect, a shard creation device may include a host processor interface circuit configured to communicate data and commands with an external host processor circuit. The devicemay include a controller processor circuit configured to merge graph data elements into merged dynamic shards, wherein the merged dynamic shards include the same number of graph data elements. The device may include a non-volatile memory configured to store data in an at least a partial graph structure, wherein the graph structure includes data elements that each include vertexes and an edge, andwherein sub-portions of the data elements are grouped into shards. A shard creation system is also provided.

Description

[0001] [Cross-reference to related applications] [0002] This application claims an application filed on December 14, 2018, entitled "OPTIMAL DYNAMIC SHARD CREATION IN STORAGE FOR GRAPHWORKLOADS" and serial number 62 / 780,186 Priority of Provisional Patent Application. The subject matter of this previously filed application is incorporated herein by reference. technical field [0003] This description relates to storage and processing of data, and more specifically, to optimal dynamic tile creation in memory banks for graphics workloads. Background technique [0004] In computer science, graph theory is the study of graphs, which are data structures used to model pairwise relationships between objects. A graph in this context consists of vertices, nodes, or points connected by edges, arcs, or lines. In computing, a graph database (GDB) is a database that uses a graph structure with nodes, edges, and attributes for semantic query to represent and store data. The key conce...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F16/901
CPCG06F16/9024G06F9/5011G06F9/5061G06F15/173G06F16/2272G06F16/2456G06F16/23G06F16/287
Inventor 赛亚迪哈尼·汉雪米李周桓奇亮奭
Owner SAMSUNG ELECTRONICS CO LTD
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