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On-chip distributed interconnection bus system and multi-core processor

An interconnected bus and distributed technology, applied in the field of data transmission, can solve the problems of system performance degradation, ring bus structure advantages are not guaranteed, etc., to achieve the effect of improving arbitration efficiency, reducing collisions, and increasing data transmission rate

Inactive Publication Date: 2020-07-10
联合华芯电子有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when the number of cores in the dual-ring bus system exceeds 24, the system performance will be reduced if the ring bus processing is added, and the advantages of the ring bus structure will not be guaranteed.

Method used

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  • On-chip distributed interconnection bus system and multi-core processor
  • On-chip distributed interconnection bus system and multi-core processor
  • On-chip distributed interconnection bus system and multi-core processor

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0042] Please refer to figure 1 and Figure 4 , the on-chip distributed interconnect bus system includes:

[0043] At least two sets of data buses transmit data to be sent by node devices through data frames;

[0044] At least one group of arbitration buses transmits multi-ary symbols of node devices through arbitration frames, the multi-ary symbols including different voltage amplitude states separated by a plurality of thresholds;

[0045] a node controller, located in the node device, the node controller is respectively connected with two sets of data buses and an arbitration bus, and is used for outputting the multi-digit symbols or the data to be sent of the node device;

[0046] The node controller compares the multi-symbol voltage with the multi-symbol voltage on the arbitration bus, and if the multi-symbol priority is higher than the multi-symbol priority on the arbitration bus, then The binary symbol is output to the arbitration bus, and the data to be sent is sent...

Embodiment 2

[0104] Please refer to Figure 5-Figure 7 , the difference between the second embodiment and the first embodiment is:

[0105] Also includes a bus repeater connected to the two groups of data buses and the arbitration bus, the bus repeater includes a node controller, a secondary arbitration bus with the same functional structure as the arbitration bus, and the two groups of data buses. Two sets of secondary data buses with the same functional structure, the node controller can be connected to the bus repeater through the secondary arbitration bus and the two sets of secondary data buses;

[0106] Specifically, the bus repeater further includes a secondary bus control module and a cache module, the secondary bus control module includes an arbitration control module and a data transmission module, the arbitration control module is connected to the secondary arbitration bus, so the data transmission module is connected to the secondary data bus;

[0107] The secondary data bus ...

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Abstract

The invention discloses an on-chip distributed interconnection bus system and a multi-core processor. The bus system comprises two groups of data buses; an arbitration bus; a node controller which outputs a multi-system symbol or to-be-sent data. If the voltage amplitude of A multi-system symbol is higher than the voltage amplitude on the arbitration bus, the multi-system symbol is outputted to the arbitration bus, and the to-be-sent data is sent to the data bus; if the to-be-sent data is transmitted in the sub-time slot, the node controller sends a multi-system symbol used for competing for the sub-time slot at the beginning of the sub-time slot; if the to-be-sent data is transmitted in the time slot, the node controller sends the multi-system symbol for competing the time slot at the beginning of the sub time slot. According to the on-chip distributed interconnection bus system and the multi-core processor provided by the invention, the arbitration efficiency of the bus is high, andthe data transmission rate of the bus is high.

Description

technical field [0001] The invention relates to the technical field of data transmission, in particular to an on-chip distributed interconnection bus system and a multi-core processor. Background technique [0002] With the rapid development of the information industry, the single-core processor appears to be incapable of transmitting large amounts of data at a high rate, exposing its limitations. It is under this premise that Stanford University first initiated research on multi-core processors in 1996, after more than 20 years of research and development. Multiple cores can be embedded in a single SoC, ranging from 8 to 32 cores in the latest AMD Ryzen Threadripper processors, and up to 28 cores in Intel Xeon W processors. In the mobile phone industry, which is closely related to public life, the number of processor cores for new mobile phones has also increased to as many as 6 to 8 cores. It can be seen that the multi-core technology meets the needs of the public life f...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/173G06F15/78G06F13/376G06F13/40
CPCG06F15/17306G06F15/7807G06F13/376G06F13/4031
Inventor 不公告发明人
Owner 联合华芯电子有限公司
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