Processor core verification method and system based on synchronous execution and medium

A technology of processor core and verification method, applied in the direction of electrical digital data processing, special data processing applications, instruments, etc., to achieve the effects of easy implementation, accurate positioning, and reduced impact

Active Publication Date: 2020-07-10
超睿科技(长沙)有限公司
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  • Abstract
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  • Claims
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Problems solved by technology

Usually this analysis process needs to be repeated many times, and it takes many weeks or even months

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  • Processor core verification method and system based on synchronous execution and medium
  • Processor core verification method and system based on synchronous execution and medium
  • Processor core verification method and system based on synchronous execution and medium

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Embodiment Construction

[0030] Such as figure 1 As shown, the implementation steps of the processor core verification method based on synchronous execution in this embodiment include:

[0031] 1) Send an initialization signal to the reference core and the verified design core to complete the initialization of the reference core and the design core;

[0032] 2) The reference core and the verified design core execute instructions in lockstep, and compare the instruction operation results of the reference core and the design core during the synchronous execution of instructions by the reference core and the design core, and compare the inconsistencies in the instruction operation results content output. The definitions of design cores and reference cores involved in this embodiment are explained as follows:

[0033] Design core: It is a design that needs to be verified. This design core is a fully functional processor core that can fetch instructions for execution, read data from the main memory, perf...

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Abstract

The invention discloses a processor core verification method and system based on synchronous execution and a medium. The processor core verification method comprises the steps: sending initializationsignals to a reference core and a verified design core to complete initialization of the reference core and the design core; executing instructions in a self-locking mode through the reference core and the verified design core, comparing instruction running results of the reference core and the design core in the process of synchronously executing the instructions through the reference core and the design core, and outputting an inconsistent content in the instruction running results. According to the invention, the error points in the verification process of the processor core system can be quickly and accurately positioned, the efficiency of the verification link can be effectively improved, the time spent in the verification link is shortened, and the method is easy to implement.

Description

technical field [0001] The invention relates to the field of processor microarchitecture design, in particular to a processor core verification method, system and medium based on synchronous execution. Background technique [0002] In microprocessor design, verification is a key link, and the degree of verification is directly related to the success or failure of the final chip. For complex microprocessors, the verification process usually performs unit-level verification at the smaller block level, and then integrates for system-level verification. Unit-level verification can be carried out by building a separate verification environment, such as the currently popular UVM (Universal Verification Methodology) method. After sufficient verification at the unit level, all modules are integrated together for system-level verification. System-level verification usually starts with a short program. Because the program is small, the number of instructions is usually hundreds of t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/398G06F115/02
CPCY02D10/00
Inventor 施军叶晨
Owner 超睿科技(长沙)有限公司
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