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Forming method of semiconductor device

A semiconductor and device technology, which is applied in the field of semiconductor device formation, can solve the problems such as difficult to keep the height of metal gate consistent, and the electrical performance of the device is reduced, so as to achieve the effect of improving electrical performance and accurate height and dimension

Active Publication Date: 2020-07-10
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When the metal gates are subsequently processed, it is difficult to keep the height of each metal gate consistent, resulting in a decrease in the electrical performance of subsequent devices

Method used

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  • Forming method of semiconductor device
  • Forming method of semiconductor device
  • Forming method of semiconductor device

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Embodiment Construction

[0024] As mentioned above, there is a problem that the top surface of the remaining gate structure is uneven when adjusting the height of the gate structure in the existing technology.

[0025] After research, it is found that the reason for the above problems is that the material of the gate is different from that of the high-k dielectric layer or the work function layer. Therefore, after the subsequent direct etching of the gate structure, the etching process has a negative effect on the gate and the high-k dielectric layer. The etch rate of the dielectric layer or the work function layer is different, resulting in an uneven top of the final gate structure.

[0026] In order to solve this problem, the present invention provides a method for forming a semiconductor device. Before etching the gate structure, an interlayer dielectric layer with a uniform material is etched to make the remaining interlayer dielectric layer have a certain height. This height is also The final hei...

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Abstract

The invention discloses a method for forming a semiconductor device, and the methodcomprises the following steps: providing a plurality of fin parts and a plurality of gate structures, correspondinglyforming the gate structures at the tops of the fin parts, and ensuring that the heights of the tops of at least two gate structures are different; forming an interlayer dielectric layer between adjacent gate structures; etching part of the interlayer dielectric layers on the two sides of each gate structure to enable the tops of the remaining interlayer dielectric layers to be flush; removing part of the gate structure to enable the top of the remaining gate structure to be alignedwith the top of the remaining interlayer dielectric layer; and etching part of the gate structure to form groovesat the top of the gate structure, and the grooves are equal in depth. According to the invention,the interlayer dielectric layer is etched firstly, so the remaining interlayer dielectric layer has atarget height, the tops of the remaining interlayer dielectric layers are flush, and finally, the tops of the remaining gate structures are aligned.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor device. Background technique [0002] With the development of technology in the semiconductor field, the size of the gate structure is continuously reduced, and at the same time, the material of the gate is changed from the traditional polysilicon to the currently widely used metal material. Generally, materials such as a high-k dielectric layer and a work function layer are formed around the metal gate to ensure the smooth realization of the function of the metal gate. [0003] When forming the metal gate structures, the top surfaces of the multiple metal gate structures are generally uneven, and the tops of the interlayer dielectric layers formed between the metal gate structures are also uneven. When the metal gates are subsequently processed, it is difficult to keep the height of each metal gate consistent, resulting in a decrea...

Claims

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Application Information

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IPC IPC(8): H01L21/8234
CPCH01L21/823431
Inventor 张城龙徐志贤
Owner SEMICON MFG INT (SHANGHAI) CORP
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