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Receiver recovering signal clock from received data signal, and clock recovery method implemented in receiver

A technology for receiving data and recovering a clock, which is applied in the field of receivers implementing the clock recovery method, and can solve the problems of occupying space and power consumption.

Active Publication Date: 2020-07-14
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, existing techniques require complex receiver front-end components that take up space and consume power

Method used

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  • Receiver recovering signal clock from received data signal, and clock recovery method implemented in receiver
  • Receiver recovering signal clock from received data signal, and clock recovery method implemented in receiver
  • Receiver recovering signal clock from received data signal, and clock recovery method implemented in receiver

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Embodiment Construction

[0052] Aspects of the invention generally address one or more issues related to the complexity and power consumption of receiver front-end components used to recover clocks from received data signals.

[0053] Traditional clock recovery schemes implemented in receivers such as 4-level pulse amplitude modulation (PAM) receivers and high-speed optical data receivers require complex front-end architectures that occupy a large area within the receiving chip and consume a large amount of power .

[0054] Referring now to the accompanying drawings, Figure 1a and Figure 1b represent transitions between binary and quaternary symbols received at the receiver, respectively. exist Figure 1a , the data samples at time(n-1) and time(n), identified as "D[n-1]" and "D[n]", can have logical values ​​0 or 1. The delay between D[n-1] and D[n] is called the unit interval (UI), and the data samples D[n-1] and D[n] are most easily detected at the center of the corresponding UI. Between time ...

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Abstract

The present disclosure relates to a receiver and to a method implemented in the receiver for recovering a signal clock from a received data signal. Successive edge transitions between successive datasamples of the received data signal are detected according to a clock recovered in the receiver. The recovered clock is adjusted based on a combination of weights assigned to at least some edge transitions among the plurality of successive edge transitions. In particular, (i) each very early transition is assigned a first weight having a first sign, (ii) each early transition is assigned a secondweight having the first sign, (iii) each late transition is assigned a third weight having a second sign opposite from the first sign, and (iv) each very late transition is assigned a fourth weight having the second sign.

Description

[0001] cross reference [0002] This application claims prior precedence to U.S. Patent Application No. 15 / 809,065, filed November 10, 2017, entitled "Receiver for Recovering Signal Clock from Received Data Signal and Clock Recovery Method Implemented in Receiver" Priority application is hereby incorporated by reference in its entirety. technical field [0003] The invention relates to the technical field of digital communication, in particular to a method for recovering a clock from a received data signal implemented in a receiver and a receiver for implementing the clock recovery method. Background technique [0004] In many technologies, a digital data stream is transmitted without a clock signal, so clock recovery is required at the receiving end to retrieve the transmitted data. Finally, the receiver generates a clock from an approximate reference frequency and phase aligns the generated clock with the data stream. This process is called clock-data recovery (CDR). ...

Claims

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Application Information

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IPC IPC(8): H04L7/00H03K5/125
CPCH04L7/033H04L7/0334H04L7/0337H04L25/06
Inventor 贝扎德·德拉奇沙岩·沙赫拉米安
Owner HUAWEI TECH CO LTD
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