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Multi-wafer stacking trimming method

A wafer and trimming technology, applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as the inability to meet the needs of multi-wafer bonding and trimming, and achieve the effect of ensuring completeness and smoothness

Active Publication Date: 2020-07-17
WUHAN XINXIN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Whether in terms of economic cost or process difficulty, the traditional trimming process cannot meet the trimming requirements of multi-wafer bonding

Method used

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  • Multi-wafer stacking trimming method
  • Multi-wafer stacking trimming method
  • Multi-wafer stacking trimming method

Examples

Experimental program
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Embodiment 2

[0082] In the subsequent step S4 of processing each wafer in the second embodiment, the trimming of the edge region of the i-th wafer after the backside thinning is satisfied, and the trimming width in the lateral direction (perpendicular to the thickness direction) is not Greater than the edge trimming width W of the second wafer after backside thinning D2 , that is, when 2≤i≤N, W Di ≤W D2 . In this way, the trimming in all wafer processing processes in Embodiment 2 is limited to W D2 In the range.

[0083] In the second embodiment, by filling the top filling layer, compared with the first embodiment, the trimming of the wafer is controlled to a smaller range. Exemplarily, the wafer trimming width can be controlled to within 10 mm by using the multi-wafer stack trimming method in Embodiment 1, and the wafer trimming width can be controlled to 5 mm by using the multi-wafer stack trimming method in Embodiment 2 within. Embodiment 2 The wafer trimming is controlled to W D...

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Abstract

The invention provides a multi-wafer stacking trimming method, which comprises the following steps: trimming an ith wafer, bonding the ith wafer with an (i-1)th wafer for thinning, and trimming the edge region of the stacked ith wafers to form a wafer stack with a good edge; and filling a bottom filling layer. Due to the existence of the bottom filling layer, the defects in the edges generated after the adjacent subsequent wafers and the stacked i wafers are bonded and thinned move outwards, the trimming width of the adjacent subsequent wafers is set to be small, support is provided for bonding and thinning of the adjacent subsequent wafers, and splitting during thinning is avoided; therefore, the trimming width of the subsequent wafer adjacent to the ith wafer is not greater than the edgetrimming width of the second wafer with the thinned back surface, and the defects in the edge after the subsequent wafer adjacent to the ith wafer and the stacked ith wafers are bonded and thinned can be removed, Wdi being smaller than or equal to Wd2; and trimming in the wafer processing process is limited within the range of Wd2, so that the trimming width of the wafer is reduced, and the effective area of the wafer is increased.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a multi-wafer stacking trimming method. Background technique [0002] In some existing semiconductor processes, such as 3D-IC wafer bonding and subsequent wafer thinning processes, in order to ensure the integrity and smoothness of the wafer edge, the wafer needs to be trimmed (Trim). [0003] Before bonding two adjacent wafers, one of the wafers needs to be trimmed for the first time, and then the two adjacent wafers are bonded. The top wafer is first ground and thinned, and then acid Etching is combined with a second trimming process to obtain ideal edges. [0004] In the multi-wafer stacking process, the previous steps are repeated. Since the bottom of the wafer that is added to the top layer needs to be fully supported during the grinding process, otherwise the edge of the grinding process will be broken. Trimming is required, and the tr...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/67H01L21/60H01L21/50
CPCH01L21/50H01L21/67121H01L2021/60007
Inventor 叶国梁刘天建
Owner WUHAN XINXIN SEMICON MFG CO LTD
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