Multi-wafer stack trimming method
A wafer and trimming technology, which is applied in the manufacturing of electrical components, circuits, semiconductor/solid-state devices, etc., and can solve problems such as the inability to meet the needs of multi-wafer bonding and trimming.
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 2
[0082] In the subsequent step S4 of processing each wafer in the second embodiment, it is all satisfied that the edge region of the i-th wafer whose back surface is thinned is trimmed, and the trimming width is different in the lateral direction (perpendicular to the thickness direction). Greater than the edge trimming width W of the second wafer after backside thinning D2 , that is, when 2≤i≤N, W Di ≤W D2 . In this way, the trimming in all wafer processing processes in the second embodiment is limited to W. D2 In the range.
[0083] In the second embodiment, by filling the top filling layer, the wafer trimming is controlled to a smaller range than that in the first embodiment. Exemplarily, using the multi-wafer stacking trimming method of the first embodiment can control the wafer trimming width to within 10 mm, and using the multi-wafer stacking trimming method of the second embodiment can control the wafer trimming width to 5 mm within. Embodiment 2 Controlling wafer ...
PUM

Abstract
Description
Claims
Application Information

- R&D
- Intellectual Property
- Life Sciences
- Materials
- Tech Scout
- Unparalleled Data Quality
- Higher Quality Content
- 60% Fewer Hallucinations
Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.
© 2025 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com