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Semiconductor packaging piece and manufacturing method thereof

A manufacturing method and semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve the problem of high cost of wafer-level packaging technology, achieve batch production, improve utilization rate, The effect of improving the yield rate

Inactive Publication Date: 2020-08-18
SHANGHAI TIANMA MICRO ELECTRONICS CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In order to meet the needs of advanced technology, the existing technology mostly uses wafer-level packaging (FOWLP) technology, but the cost of wafer-level packaging technology is relatively high

Method used

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  • Semiconductor packaging piece and manufacturing method thereof
  • Semiconductor packaging piece and manufacturing method thereof
  • Semiconductor packaging piece and manufacturing method thereof

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Embodiment Construction

[0046] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, but not to limit the present invention. In addition, it should be noted that, for the convenience of description, only some structures related to the present invention are shown in the drawings but not all structures.

[0047] First, a conventional method of manufacturing a semiconductor package will be described. figure 1 It is a schematic top view structure diagram of an existing wafer, figure 2 It is a schematic cross-sectional structure diagram of a semiconductor package formed in each step of an existing manufacturing method of a semiconductor package. figure 2 The structure of the semiconductor package formed in each step is along the figure 1 The cross-sectional structure of A-A. see figure 1 and figure 2 , the man...

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PUM

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Abstract

The embodiment of the invention discloses a semiconductor packaging piece and a manufacturing method thereof. The manufacturing method comprises the steps of providing a first substrate; manufacturingat least two first wiring layers on one side of the first substrate; arranging a first insulating layer between every two adjacent first wiring layers, and patterning the first insulating layers to form a plurality of first through holes, wherein every two adjacent first wiring layers are electrically connected through the corresponding first through holes, and the at least two first wiring layers are used as wiring structures of the semiconductor packaging piece; providing at least one semiconductor element, wherein each semiconductor element comprises a plurality of pins; arranging the side, which is provided with the pins, of the semiconductor element on the side, which is away from the first substrate, of the wiring structure; plastically packaging the semiconductor element; and planting balls on the side, which is away from the semiconductor element, of the wiring structure. Compared with the prior art, the embodiment of the invention realizes low cost and high yield on the basisof high precision.

Description

technical field [0001] Embodiments of the present invention relate to the technical field of semiconductor packaging, and in particular, to a semiconductor package and a manufacturing method thereof. Background technique [0002] With the development of advanced technologies such as artificial intelligence, 5G technology and smart phones, the requirements for semiconductor technology are getting higher and higher, driving and promoting the development of the semiconductor industry. [0003] In semiconductor technology, semiconductor packaging technology has played an important role in the development of the semiconductor industry. Semiconductor packaging needs to achieve smaller form factors, lighter, thinner, more pins, high reliability and lower cost. In order to meet the needs of advanced technologies, the prior art mostly adopts a wafer-level packaging (FOWLP) technology, but the cost of the wafer-level packaging technology is relatively high. Contents of the inventio...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/31H01L23/498H01L21/56H01L25/07
CPCH01L23/3128H01L23/49816H01L23/49838H01L21/56H01L25/072H01L2924/181H01L2224/16225H01L2924/15311H01L2224/97H01L2924/15174H01L23/49822H01L21/4857H01L21/6835H01L2221/68345H01L2221/68359H01L21/561H01L2924/00012H01L21/4853H01L21/486H01L21/4896H01L24/81H01L24/96H01L24/97H01L2924/37001
Inventor 彭旭辉席克瑞崔婷婷秦锋张劼
Owner SHANGHAI TIANMA MICRO ELECTRONICS CO LTD