Architecture and device for multi-stream vision processing on shared devices
A technology of equipment and processing equipment, which is applied in the field of computer systems and can solve problems such as poor synchronization of calculations, high cost, and loss of processing power.
Active Publication Date: 2020-08-21
GM GLOBAL TECH OPERATIONS LLC
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- Abstract
- Description
- Claims
- Application Information
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Problems solved by technology
Computations on these devices, CPUs, and accelerators may not be well synchronized for multiple perceptual streams, resulting in loss of processing power and higher costs
Method used
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[0043] The following detailed description is merely exemplary in nature and not intended to limit application and use. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, brief summary or the following detailed description. As used herein, the term "module" refers to any hardware, software, firmware, electronic control component, processing logic, and / or processor device, alone or in any combination, including but not limited to: application specific integrated circuits (ASICs), Field Programmable Gate Arrays (FPGAs), electronic circuits, processors (shared, dedicated, or group) and memory executing one or more software or firmware programs, combinational logic circuits, and / or other suitable components that provide the described functionality.
[0044] Embodiments of the disclosure may be described herein in terms of functional and / or logical block components and various processing steps. I...
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A stream manager for managing the distribution of instructions to a plurality of processing devices includes a dispatcher module configured to: receive multiple instruction streams, wherein each instruction stream includes a plurality of requested computations for processing perception data from a perception data source; partition each instruction stream into a plurality of partitions based on type of device to perform a requested computation from the instruction stream; assign a release time and deadline to each partition, and dispatch partition computations to a plurality of scheduling queues to distribute processing of the partition computations amongst the plurality of processing devices. The plurality of scheduling queues include: a plurality of CPU schedulers, wherein each CPU scheduler is assigned to a specific CPU and a specific scheduling queue; and a plurality of accelerator schedulers, wherein each accelerator scheduler is assigned to a specific scheduling queue and a specific type of accelerator.
Description
technical field [0001] The technology described in this patent document relates generally to computer systems, and more specifically to computer system architectures that allow for sharing of processing resources. Background technique [0002] Advanced autonomous vehicle (AV) and advanced driver assistance systems (ADAS) applications utilize multiple sensing devices, such as cameras, and thus process data from multiple sensing devices. The processing of the sensory stream from the sensory device may involve computations of both CPU (Central Processing Unit) and accelerators (eg GPU, DSP, FPGA). When multiple perceptual streams require computation, the processing of multiple perceptual streams may involve the computation of multiple CPUs and accelerators, which are usually shared by multiple perceptual streams. For multiple perceptual streams, computations on these devices, CPUs, and accelerators may not be well synchronized, resulting in loss of processing power and higher ...
Claims
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IPC IPC(8): G06F9/50H04L47/52H04L47/6275
CPCG06F9/5038G06F9/4887G06V20/56G06V10/96H04L47/6275H04L47/52H04L47/6295H04L67/60
Inventor S.王U.D.博尔多洛伊S.G.路斯科S.N.麦金尼
Owner GM GLOBAL TECH OPERATIONS LLC