Layout structure of dynamic random access memory and fabrication method of photomask

Abstract

The invention discloses a layout structure of a dynamic random access memory, which includes a plurality of word line patterns, a plurality of active area patterns and a plurality of contact patterns. The word line patterns extend along the first direction and are arranged in parallel along the second direction. The active area pattern crosses the two word line patterns and is divided into a middle portion and two end portions. The shape of the middle part is a parallelogram including a pair of obtuse angles and a pair of acute angles. The contact pattern overlaps a middle portion of the active area pattern, and includes a pair of first edges parallel to the first direction and a pair of second edges between the first edges, wherein the second edges include a stepped shape. One purpose of the present invention is to improve the cutting process of the active area and / or the margin of the bit line contact plug process, so as to improve the cutting accuracy of the active area and / or reduce the bit line (bit line) and the adjacent storage space. Short-circuit defects between storage node contacts improve product yield.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a layout structure of a dynamic random access memory and a method for manufacturing a photomask used in the technology of the dynamic random access memory. Background technique [0002] Dynamic random access memory (DRAM) is a kind of volatile memory, including an array area (array area) composed of multiple memory cells (memory cells) and a peripheral area (peripheral area) composed of control circuits . Each memory cell includes a transistor electrically connected to a capacitor, and the transistor controls the storage or release of charges in the capacitor to achieve the purpose of storing data. The control circuit can be positioned to each memory cell to control its data access through word lines (word line, WL) and bit lines (bit line, BL) that span the array area and are electrically connected to each memory cell. [0003] In the advanced semiconductor process, the...

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Problems solved by technology

[0003] In the advanced semiconductor process, the layout pattern of the memory is getting closer and closer to obtain a higher density per unit area, but this not only increases the difficulty of manufacturing, but also the tolerance of the memory element to the variation of the manufacturing process is becoming more and more Strict, process variations in key steps may cause electrical abnormalities in components

For example, in the active region cut process, the size of the active region after cutting is often shifted due to the deformation of the opening pattern.

In addition, the current DRAM adopting a buried wordline structure often causes the bit line to contact the adjacent storage node due to the insufficient recess of the active area where the bit line contacts the plug contact. A short circuit occurs between the plugs (storage nodecontact), resulting in abnormal memory function

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