Communication method of time schedule controller and power management chip and driving structure
A technology of power management chips and timing controllers, which is applied to instruments, static indicators, etc., and can solve the problems of occupying pins, wiring area, and large production costs.
Active Publication Date: 2020-09-18
SHENZHEN CHINA STAR OPTOELECTRONICS TECH CO LTD
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Problems solved by technology
It is rarely used at ordinary times, and it is only used in special cases, so it occupies the pins of the timing controller and power management chip, resulting in a larger wiring area and production cost.
Method used
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[0029] The terms “first”, “second”, etc. in the description and claims of the embodiments of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific sequence or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments described herein can be implemented in an order other than the content illustrated or described herein. The technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative work fall within the protection s...
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The invention discloses a communication method for a time schedule controller and a power management chip, and the method comprises the steps: collecting a write protection signal line signal, determining a level signal of a write protection signal line according to the write protection signal line signal to obtain a write protection level signal, the write protection signal line being a first signal line; when the write protection level signal is a low level signal, enabling the time schedule controller to use a first protocol, and enabling the power management chip to output a first voltage;and when the write protection level signal is a high level signal, enabling the time schedule controller to use a second protocol, and enabling the power management chip to output the first voltage or a second voltage. According to the embodiment of the invention, by reducing the voltage selection pins, the multiplexing and writing protection signal lines and the bidirectional data lines and clock signal lines of an integrated circuit bus, the same signal line can perform transmission according to different protocols, so that the number of pins of the time schedule controller is reduced, andthe wiring area and the production cost occupied by the time schedule controller are reduced.
Description
Technical field [0001] The embodiments of the present application relate to the field of display technology, and in particular, to a communication method and drive structure between a timing controller and a power management chip. Background technique [0002] With the development of technology, mobile phones, televisions, personal digital assistants, digital cameras, notebook computers, desktop computers and other devices have increasingly become indispensable electronic devices in people's life and work. Regardless of whether it is a mobile phone or a tablet, these electronic devices are equipped with a display device. The display device generally includes a display panel (Panel) and an external drive circuit. The external drive circuit generally includes: a printed circuit board (Printed Circuit). Board, PCB) timing controller (TCON), power management chip (Power manage IC, PMIC) and programmable gamma correction chip (P-gammaIC), etc., wherein the timing controller is mainly ...
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Login to View More IPC IPC(8): G09G3/36
CPCG09G3/36G09G2370/14G09G2370/10
Inventor 肖光星
Owner SHENZHEN CHINA STAR OPTOELECTRONICS TECH CO LTD