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Substrate processing apparatus

A substrate and pattern technology, which is applied to the original parts for opto-mechanical processing, semiconductor/solid-state device parts, instruments, etc., can solve the problems of partition waste, low degree of freedom of alignment mark configuration, etc., to improve the degree of freedom and suppress the configuration. area effect

Active Publication Date: 2020-09-29
KIOXIA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] When setting calibration marks on the original plate and the material to be processed, the degree of freedom in the arrangement of the calibration marks is low, and sometimes wasteful areas are generated in the partitions where the calibration marks are arranged

Method used

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  • Substrate processing apparatus
  • Substrate processing apparatus
  • Substrate processing apparatus

Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach 1

[0055] use Figure 1 to Figure 13 Embodiment 1 will be described. The alignment mark of Embodiment 1 is used, for example, during imprint processing. First, an imprint apparatus that performs imprint processing, operations of the imprint apparatus, and the like will be described below.

[0056] (Example of configuration of imprinting device)

[0057] figure 1 It is a diagram showing a configuration example of the imprint apparatus 1 according to the first embodiment. Such as figure 1 As shown, the imprint apparatus 1 includes a template stage 81 , a mounting stage 82 , a reference mark 85 , a calibration sensor 86 as a calibration unit, a droplet device 87 , a stage base 88 , a light source 89 , and a control unit 90 . A template 10 as an original for transferring a fine pattern to a resist (resist) as a film to be transferred on a wafer 20 is attached to the imprint apparatus 1 .

[0058] The mounting table 82 includes a wafer chuck (chuck) 84 and a main body 83 . The ...

Embodiment approach 2

[0157] use Figure 14 ~ Figure 23 Embodiment 2 will be described. The case where the alignment mark of the second embodiment is used for imprint processing is also taken as an example.

[0158] In the above-mentioned first embodiment, for example, the calibration mark extended greatly in the X direction and compressed in the Y direction has been described. Thereby, the degree of freedom of arrangement of the calibration marks can be increased, and the arrangement area can be suppressed.

[0159] On the other hand, in the above-mentioned calibration mark using a moiré image generated by a periodic structure, it is impossible to accurately detect a certain amount of displacement or more as a problem caused by the periodic structure.

[0160] For example, let P be the characteristic period of the periodic structure of the moiré mark, that is, the structural period, let the magnification of the displacement amount in the moiré image be M, and let the number of moiré fringes requ...

Deformed example 1

[0213] In the above-mentioned second embodiment, the duty ratio of the detection units 16Xp, 16Yp of the X marker 16X and the Y marker 16Y is set to 2:2, for example, but when the duty ratio is D:2 (D>2) In this way, the pattern configuration of the X mark and the Y mark on the wafer can be made more complicated, and higher functions can be provided. exist Figure 19 A configuration example of the X marks 17X, 27Xa in the case of D=4 is shown in .

[0214] Figure 19 It is a schematic diagram showing an example of the configuration of a template constituting an overlay mark and X marks 17X, 27Xa of a wafer according to Modification 1 of Embodiment 2. Such as Figure 19 As shown, the respective moiré portions 17Xm and 27Xma of the X marks 17X and 27Xa are configured to have a duty ratio of 1:1 in the same manner as in the example of Embodiment 2 described above.

[0215] The duty ratio of the detection part 17Xp in the X mark 17X of the template is 4:2, the part correspondi...

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PUM

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Abstract

The invention discloses a substrate processing apparatus. In accordance with a calibration mark of an embodiment, a first pattern includes a first portion and a second portion. A second pattern includes a third portion and a fourth portion. The first portion and the third portion partially overlap each other. The second portion and the fourth portion partially overlap each other. The larger one ofthe structural periods of the first portion and the third portion is equal to or less than 1.2 times the smaller one. The second portion and the fourth portion have the same structure period and areat least twice the structure period of the smaller one of the structure periods of the first portion and the third portion, a duty ratio of the first portion and the third portion, which is a ratio ofthe light shielding portion to the light transmitting portion, is 1: 1, a duty ratio of the second portion is D: 2, and D is an integer of 2 or more.

Description

[0001] This application is based on and claims the benefit of priority of the prior Japanese Patent Application No. 2019-050733 filed on March 19, 2019, the entire contents of which are hereby incorporated by reference. technical field [0002] Embodiments of the present invention relate to an alignment mark (Alignment mark), an imprint (Imprint) method, a manufacturing method of a semiconductor device, and an alignment device. Background technique [0003] As a method of forming a fine pattern in the manufacturing process of a semiconductor device, imprint processing, proximity exposure processing, or near-field lithography (lithography) processing is performed. [0004] In such processing, alignment processing is performed between an original plate such as a template or a reticle and a workpiece. The alignment process is performed, for example, using alignment marks respectively provided on the original plate and the material to be processed. [0005] When calibration mar...

Claims

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Application Information

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IPC IPC(8): G03F9/00G03F7/00H01L23/544H01L21/68
CPCG03F9/7076G03F7/0002H01L23/544H01L21/68H01L2223/54426G03F9/7042G03F1/42H01L21/0271G03F7/70141H01L21/027G03F9/7088G03F9/7015
Inventor 三木聪
Owner KIOXIA CORP