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Panel and pixel structure thereof

A pixel structure and panel technology, applied in nonlinear optics, instruments, optics, etc., can solve the problems of inability to increase the filling rate and high parasitic capacitance, and achieve the effect of improving the filling rate and reducing the parasitic capacitance.

Active Publication Date: 2020-10-09
HANNSTOUCH SOLUTION
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The technical problem to be solved by the present invention is that the parasitic capacitance of the pixel structure is too high, and the filling rate cannot be increased when the size of the pixel structure is reduced.

Method used

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  • Panel and pixel structure thereof
  • Panel and pixel structure thereof
  • Panel and pixel structure thereof

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Embodiment Construction

[0044] Please refer to figure 2 , which is a schematic top view of a panel according to an embodiment of the present invention. Such as figure 2 As shown, the panel PL of this embodiment may include a plurality of pixel structures 100 corresponding to pixels or sub-pixels of an image, respectively. For example, each pixel structure 100 can be used to display a pixel or sub-pixel of a single color of an image or to detect a pixel or sub-pixel of a received image. Specifically, the panel PL may have a plurality of pixel regions PR for respectively defining the region of each pixel structure 100 . In this embodiment, there is no gap between adjacent pixel regions PR, that is, the adjacent edges of adjacent pixel regions PR are coincident, so that the pixel region PR can represent the size of a single pixel structure 100 . In this embodiment, the pixel regions PR are arranged in an array, but not limited thereto.

[0045] To clarify each pixel structure 100, figure 2 Only ...

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Abstract

The invention discloses a pixel structure. The pixel structure comprises a substrate, a scanning line arranged on the substrate along a first direction, a data line arranged on the substrate along a second direction different from the first direction, and a pixel electrode arranged on the substrate. The data line and the scanning line are staggered, and the scanning line and / or the data line and the pixel electrode are staggered. Therefore, the parasitic capacitance of the pixel structure can be reduced, and the filling rate of the pixel structure can be improved.

Description

technical field [0001] The invention relates to a panel and its pixel structure, in particular to a panel with reduced total parasitic capacitance and its pixel structure. Background technique [0002] The pixel structure is generally applied to a display panel to display image frames. With the increasing requirement for image resolution, the size of the pixel structure needs to be continuously reduced, so that the influence of the parasitic capacitance in the pixel structure on the design of the pixel structure is more obvious. In order to reduce the parasitic capacitance, the fill factor of the pixel structure, that is, the ratio of the area of ​​the pixel electrode to the area of ​​the pixel region, is therefore reduced. [0003] Please refer to figure 1 , which is a schematic top view of an existing pixel structure. Such as figure 1 As shown, the existing pixel structure 10 is defined as a structure located in the pixel region PR, and the scanning line 12 and the dat...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G02F1/1362
CPCG02F1/136286G02F1/136213
Inventor 林圣佳
Owner HANNSTOUCH SOLUTION