Preparation method of field effect transistor, field effect transistor and semiconductor substrate

Abstract

The invention provides a preparation method of a fin type field effect transistor, the field effect transistor and a semiconductor substrate, which can reduce the GIDL current of the field effect transistor under the condition of meeting the small-size requirement of the field effect transistor. The preparation method comprises the steps: providing a semiconductor substrate, laying a gate dielectric layer on at least one part of the semiconductor substrate, and arranging a gate structure and a side wall on the gate dielectric layer, wherein the side wall at least covers the side wall of the gate structure, the semiconductor substrate in a preset region below the gate dielectric layer and the semiconductor substrate on the outer side of the preset region form a step; arranging an isolationlayer, wherein the isolation layer covers part of the side wall of the step; and configuring a source electrode and a drain electrode on the semiconductor substrate, wherein the top surfaces of the source electrode and the drain electrode are flush with the step. According to the invention, the isolation layer is used for blocking on the transmission path of the GIDL current, so the GIDL current of the field effect transistor can be reduced under the condition that the small-size requirement of the field effect transistor is met.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing and processing. More specifically, the invention relates to a method for preparing a field effect transistor, a field effect transistor and a semiconductor substrate. Background technique [0002] With the rapid development of VLSI technology, the size of field effect transistors is constantly decreasing. Due to the sharp reduction in the size of the field effect transistor, the thickness of the gate oxide layer is reduced to 2nm or even thinner. While the size of the device is scaled down, the working voltage is not proportionally reduced accordingly, which makes the channel electric field and oxide layer electric field of the device significantly increased, and the reliability problem of the device caused by the thin gate becomes increasingly prominent. [0003] In field effect transistors, gate-induced drain leakage (GIDL) has a great influence on the reliability of field effect tran...

AI Technical Summary

Problems solved by technology

While the size of the device is scaled down, the operating voltage is not reduced correspondingly, which makes the channel electric field and oxide layer electric field of the device significantly increased, and the reliability problem of the device caused by the thin gate is becoming more and more prominent.

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