Dynamic random access memory

Abstract

The invention provides a dynamic random access memory. The dynamic random access memory comprises a substrate, a plurality of transistors, a plurality of bit line sets, a plurality of conductive structures and a plurality of word line sets, wherein the plurality of transistors are arranged on the substrate in an array, and each transistor sequentially comprises a first conductive layer, a second conductive layer and a third conductive layer from bottom to top; the plurality of bit line sets are arranged on the substrate in parallel in the Y direction and penetrate through the transistors, andeach bit line set comprises a first bit line and a second bit line which are electrically connected with the first conductive layer of the corresponding transistor; the plurality of conductive structures are located in the plurality of transistors, and the conductive structures are electrically connected with the second conductive layers of the transistors and the substrate; and the plurality of word line sets are arranged on the substrate in parallel in the X direction, and each word line set comprises a first word line and a second word line which are respectively arranged on the side wall of each transistor.

Description

technical field [0001] The invention relates to a memory, in particular to a dynamic random access memory. Background technique [0002] on 4F 2 In an array-arranged DRAM, vertical transistors with embedded word lines and capacitors stacked on them constitute the memory cell area, but the structure of this type of vertical transistors will produce floating body effects. This will further lead to problems such as threshold voltage fluctuation, memory effect or hysteresis effect, which will reduce the reliability of the product. Contents of the invention [0003] The invention provides a dynamic random access memory, including: a substrate, a plurality of transistors, a plurality of bit lines, a plurality of conductive structures and a plurality of word lines. A plurality of transistor arrays are arranged on the base, and each transistor includes a first conductive layer, a second conductive layer and a third conductive layer sequentially from bottom to top. A plurality o...

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Problems solved by technology

[0002] on 4F 2 In an array-arranged DRAM, vertical transistors with embedded word lines and capacitors stacked on them constitute the memory cell area, but the structure of this type of vertical transistors will produce floating body effects. This will lead to problems such as threshold voltage fluctuation, memory effect or hysteresis effect, which will reduce the reliability of the product

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